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| Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems ADVANCED COMMUNICATIONS Description FINAL Features DATASHEET ACS8522 SETS LITE The ACS8522 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and Frame Synchronization clocks. The ACS8522 is fully compliant with the required international specifications and standards. The device supports Free-run, Locked and Holdover modes, with mode selection controlled either automatically by an internal state machine or forced by register configuration. The ACS8522 accepts up to four independent input SEC reference clock sources from Recovered Line Clock, PDH network, and Node Synchronization. The ACS8522 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock, both with programmable pulse width and polarity. The ACS8522 includes a Serial Port, which can be SPI compatible, providing access to the configuration and status registers for device setup. The ACS8522 supports IEEE 1149.1[5] JTAG boundary scan. The User can choose between OCXO or TCXO to define the Stratum and/or Holdover performance required. Suitable for Stratum 3, 4E, 4 and SONET Minimum Clock (SMC) or SONET/SDH Equipment Clock (SEC) applications (to Telcordia 1244-CORE[19] Stratum 3 and GR-253[17], and ITU-T G.813[11] Options and specifications) Accepts four individual input reference clocks, all with robust input clock source quality monitoring Simultaneously generates four output clocks, plus two Sync pulse outputs Absolute Holdover accuracy better than 3 x 10-10 (manual), 7.5 x 10-14 (instantaneous); Holdover stability defined by choice of external XO Programmable PLL bandwidth, for wander and jitter tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps Automatic hit-less source switchover on loss of input Serial SPI compatible interface Output phase adjustment in 6 ps steps up to 200 ns IEEE 1149.1[5] JTAG Boundary Scan Available in LQFP 64-pin package Single 3.3 V operation. 5 V tolerant Lead (Pb)-free version available (ACS8522T), RoHS and WEEE compliant. Block Diagram Figure 1 Block Diagram of the ACS8522 SETS LITE T4 DPLL/Freq. Synthesis Inputs: 4 x TTL Programmable; 2 kHz 4 kHz N x 8 kHz 1.544/2.048 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz T4 DPLL Selector Input Port Monitors and Selection Control Optional Divider, 1/n n = 1 to 214 PFD Digital Loop Filter DTO T4 Output APLL Frequency Dividers Output Ports O1 to O4 Output O1: PECL/LVDS Outputs O2 - 04: TTL Programmable; E1/DS1 (2.048/ 1.544 MHz) and frequency multiples: 1.5 x, 2 x, 3 x 4 x, 6 x, 12 x 16 x and 24 x E3/DS3 2 kHz 8 kHz and OC-N* rates T0 DPLL/Freq. Synthesis 4 x SEC T0 DPLL Selector Optional Divider, 1/n n = 1 to 214 Digital Loop Filter T0 Output APLL Frequency Dividers DTO T0 Feedback APLL FrSync & MFrSync 8 kHz (FrSync) 2 kHz (MFrSync) PFD TCK TDI TMS TRST TDO IEEE 1149.1 JTAG Chip Clock Generator Priority Register Set Table Serial Port OCXO or TCXO OC-N* rates = OC-1 51.84 MHz OC-3 155.52 MHz and derivatives: 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 311.04 MHz F8522P_001BLOCKDIA_04 Revision 5/November 2006 (c) Semtech Corp. Page 1 www.semtech.com Table of Contents ADVANCED COMMUNICATIONS Table of Contents Section ACS8522 SETS LITE DATASHEET Page FINAL Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 4 Pin Description........................................................................................................................................................................................... 5 Introduction................................................................................................................................................................................................ 7 General Description................................................................................................................................................................................... 7 Overview .............................................................................................................................................................................................7 Input Reference Clock Ports .............................................................................................................................................................9 Locking Frequency Modes ....................................................................................................................................................... 9 Clock Quality Monitoring................................................................................................................................................................. 10 Activity Monitoring ................................................................................................................................................................. 11 Frequency Monitoring ........................................................................................................................................................... 12 Selection of Input Reference Clock Source................................................................................................................................... 12 Forced Control Selection....................................................................................................................................................... 13 Automatic Control Selection ................................................................................................................................................. 13 Ultra Fast Switching .............................................................................................................................................................. 13 Fast External Switching Mode-SRCSW pin .......................................................................................................................... 13 Output Clock Phase Continuity on Source Switchover ....................................................................................................... 14 Modes of Operation ........................................................................................................................................................................ 14 Free-run Mode ....................................................................................................................................................................... 14 Pre-locked Mode ................................................................................................................................................................... 14 Locked Mode ......................................................................................................................................................................... 14 Lost-phase Mode................................................................................................................................................................... 14 Holdover Mode ...................................................................................................................................................................... 15 Pre-locked2 Mode ................................................................................................................................................................. 17 DPLL Architecture and Configuration ............................................................................................................................................ 17 TO DPLL Main Features ........................................................................................................................................................ 18 T4 DPLL Main Features ........................................................................................................................................................ 18 TO DPLL Automatic Bandwidth Controls.............................................................................................................................. 18 Phase Detectors .................................................................................................................................................................... 18 Phase Lock/Loss Detection.................................................................................................................................................. 19 Damping Factor Programmability......................................................................................................................................... 19 Local Oscillator Clock ............................................................................................................................................................ 20 Output Wander ...................................................................................................................................................................... 20 Jitter and Wander Transfer ................................................................................................................................................... 23 Phase Build-out ..................................................................................................................................................................... 23 Input-to-Output Phase Adjustment....................................................................................................................................... 24 Input Wander and Jitter Tolerance....................................................................................................................................... 24 Using the DPLLs for Accurate Frequency and Phase Reporting ........................................................................................ 26 MFrSync and FrSync Alignment-SYNC2K............................................................................................................................. 27 Output Clock Ports .......................................................................................................................................................................... 27 PECL/LVDS Output Port Selection ....................................................................................................................................... 27 Output Frequency Selection and Configuration .................................................................................................................. 28 Power-On Reset............................................................................................................................................................................... 38 Serial Interface................................................................................................................................................................................ 38 Revision 5/November 2006 (c) Semtech Corp. Page 2 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET Section Page Register Map........................................................................................................................................................................................... 41 Register Organization ..................................................................................................................................................................... 41 Register Access ..................................................................................................................................................................... 41 Interrupt Enable and Clear ................................................................................................................................................... 41 Defaults.................................................................................................................................................................................. 41 Register Descriptions ............................................................................................................................................................................. 45 Electrical Specifications ....................................................................................................................................................................... 105 JTAG ............................................................................................................................................................................................... 105 Over-voltage Protection ................................................................................................................................................................ 105 ESD Protection .............................................................................................................................................................................. 105 Latchup Protection........................................................................................................................................................................ 105 Maximum Ratings ......................................................................................................................................................................... 106 Operating Conditions .................................................................................................................................................................... 106 DC Characteristics ........................................................................................................................................................................ 106 Jitter Performance ........................................................................................................................................................................ 109 Input/Output Timing ..................................................................................................................................................................... 111 Package Information ............................................................................................................................................................................ 112 Thermal Conditions....................................................................................................................................................................... 113 Application Information ........................................................................................................................................................................ 114 References ............................................................................................................................................................................................ 115 Abbreviations ........................................................................................................................................................................................ 115 Trademark Acknowledgements ........................................................................................................................................................... 116 Revision Status/History ....................................................................................................................................................................... 117 Ordering Information ............................................................................................................................................................................ 118 Disclaimers.................................................................................................................................................................................... 118 Contacts......................................................................................................................................................................................... 118 Revision 5/November 2006 (c) Semtech Corp. Page 3 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Pin Diagram FINAL DATASHEET Figure 2 ACS8522 Pin Diagram Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems 1 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 AGND1 IC1 AGND2 VA1+ INTREQ REFCLK DGND1 VD1+ VD2+ DGND2 DGND3 VD3+ SRCSW VA2+ AGND3 IC2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SONSDHB IC11 IC10 IC9 IC8 O4 AGND4 VA3+ O3 O2 VDD7 DGND6 SDO TDI TDO TCK ACS8522 SETS LITE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PORB SCLK VDD6 VDD5 CSB SDI CLKE TMS DGND5 VDD4 VDD3 TRST VDD2 IC7 SEC4 SEC3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF IC3 IC4 IC5 IC6 VDD5V SYNC2K SEC1 SEC2 DGND4 VDD1 F8522D_002PINDIAG_02 Revision 5/November 2006 (c) Semtech Corp. Page 4 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Pin Description Table 1 Power Pins Pin Number 8, 9, 12 22 27 Symbol VD1+, VD2+, VD3+ VDD_DIFF VDD5V I/O P P P Type Description Supply Voltage: Digital supply to gates in analog section, +3.3 Volts 10%. Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts 10%. VDD5V: Digital supply for +5 Volts tolerance to input pins. Connect to +5 Volts (10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping. Input pins tolerant up to +5.5 Volts. Supply Voltage: Digital supply to logic, +3.3 Volts 10%. FINAL DATASHEET 32, 36, 38, 39, 45, 46, 54 4 14, 57 15, 58 7, 10, 11 31, 40, 53 21 1, 3 VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7 VA1+ VA2+, VA3+ AGND3, AGND4 DGND1, DGND2, DGND3 DGND4, DGND5, DGND6 GND_DIFF AGND1, AGND2 P - P P - Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts 10%. Supply Voltage: Analog supply to output PLLs APLL2 and APLL1, +3.3 Volts 10%. Supply Ground: Analog ground for output PLLs APLL2 and APLL1. Supply Ground: Digital ground for components in PLLs. Supply Ground: Digital ground for logic. Supply Ground: Digital ground for differential output pins 19 and 20. Supply Ground: Analog grounds. P P P P - Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Table 2 Internally Connected Pins Pin Number 2, 16, 23, 24, 25, 26, 35, 60, 61, 62, 63 Symbol IC1, IC2, IC3, IC4, IC5, IC6, IC7, IC8, IC9, IC10, IC11 I/O Type Description Internally Connected: Leave to Float. Table 3 Other Pins Pin Number 5 6 Symbol INTREQ REFCLK I/O O I Type TTL/CMOS TTL Description Interrupt Request: Active High/Low software Interrupt output. Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock). Revision 5/November 2006 (c) Semtech Corp. Page 5 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 3 Other Pins (cont...) Pin Number 13 17 18 19, 20 28 29 30 33 34 37 Symbol SRCSW FrSync MFrSync O1POS, O1NEG SYNC2K SEC1 SEC2 SEC3 SEC4 TRST I/O I O O O I I I I I I Type TTLD TTL/CMOS TTL/CMOS LVDS/PECL TTLD TTLD TTLD TTLD TTLD TTLD Description Source Switching: Force Fast Source Switching on SEC1 and SEC2. Output Reference: 8 kHz Frame Sync output. Output Reference: 2 kHz Multi-Frame Sync output. Output Reference: Programmable, default 38.88 MHz, LVDS. Multi-Frame Sync 2kHz input. Input Reference: Programmable, default 8 kHz. Input Reference: Programmable, default 8 kHz. Input Reference: Programmable, default 19.44 kHz. Input Reference: Programmable, default 19.44 kHz. JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for Boundary Scan stand-by mode, still allowing correct device operation. If not used connect to GND or leave floating. JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. If not used connect to VDD or leave floating. SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of SCLK to be active. Microprocessor Interface Address: Serial Data Input. Chip Select (Active Low): This pin is asserted Low by the microprocessor to enable the microprocessor interface. Serial Data Clock. When this pin goes High data is latched from SDI pin. Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. JTAG Clock: Boundary Scan clock input. JTAG Output: Serial test data output. Updated on falling edge of TCK. JTAG Input: Serial test data Input. Sampled on rising edge of TCK. Interface Address: SPI compatible Serial Data Output. Output Reference 2: Programmable, default 38.88 MHz. Output Reference 3: Programmable, default 19.44 MHz. Output Reference 4: Programmable, default 1.544/2.048 MHz (BITS). SONET or SDH Frequency Select: Sets the initial power-up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34 Bit 2, and Reg. 38 Bits 5 and 6. When set Low, SDH rates are selected (2.048 MHz etc.), and when set High, SONET rates are selected (1.544 MHz etc.). The register states can be changed after power-up by software. FINAL DATASHEET 41 42 43 44 47 48 49 50 51 52 55 56 59 64 TMS CLKE SDI CSB SCLK PORB TCK TDO TDI SDO O2 O3 O4 SONSDHB I I I I I I I O I O O O O I TTLD TTLD TTLD TTLU TTLD TTLU TTLD TTL/CMOS TTLD TTLD TTL/CMOS TTL/CMOS TTL/CMOS TTLD Revision 5/November 2006 (c) Semtech Corp. Page 6 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Introduction FINAL DATASHEET confines all temperature critical components to one well defined and pre-calibrated module, whose performance can be chosen to match the application; for example an TCXO for Stratum 3 applications. All performance parameters of the DPLLs are programmable without the need to understand detailed PLL equations. Bandwidth, damping factor and lock range can all be set directly, for example. The PLL bandwidth can be set over a wide range, 0.1 Hz to 70 Hz in 18 steps, to cover all SONET/SDH clock synchronization applications. The ACS8522 includes a serial port, providing access to the configuration and status registers for device setup and monitoring. The ACS8522 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and Frame/MultiFrame sync pulses. Digital Phase Locked Loop (DPLL) and direct digital synthesis methods are used in the device so that the overall PLL characteristics are very stable and consistent compared to traditional analog PLLs. In Free-run mode, the ACS8522 generates a stable, lownoise clock signal at a frequency to the same accuracy as the external oscillator, or it can be made more accurate via software calibration to within 0.02 ppm. In Locked mode, the ACS8522 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8522 generates a stable, low-noise clock signal, adjusted to match the last known good frequency of the last selected reference source. A high level of phase and frequency accuracy is made possible by an internal resolution of up to 54 bits and internal Holdover accuracy of 0.0012 ppb (1.2 x 10-12). In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.736[7], G.742[8], G783[9], G.812[10], G.813[11], G.823[13],G.824[14] and Telcordia GR-253-CORE[17] and GR-1244-CORE[19]. The ACS8522 supports all three types of reference clock source: recovered line clock, PDH network synchronization timing and node synchronization. The ACS8522 generates independent T0 and T4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. One key architectural advantage that the ACS8522 has over traditional solutions is in the use of DPLL technology for precise and repeatable performance over temperature or voltage variations and between parts. The overall PLL bandwidth, loop damping, pull-in range and frequency accuracy are all determined by digital parameters that provide a consistent level of performance. An Analog PLL (APLL) takes the signal from the DPLL output and provides a lower jitter output. The APLL bandwidth is set four orders of magnitude higher than the DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. The DPLLs are clocked by the external Oscillator module (TCXO or OCXO) so that the Free-run or Holdover frequency stability is only determined by the stability of the external oscillator module. This second key advantage Revision 5/November 2006 (c) Semtech Corp. General Description Overview The following description refers to the Block Diagram (Figure 1 on page 1). The ACS8522 SETS device has four SEC clock inputs (SEC1 to SEC4), and generates four output clocks on outputs O1 to O4. The device offers a total of 55 possible output frequencies. There are two independent paths through the device: T0 path comprising T0 DPLL and T0 Output and Feedback APLLs, and T4 path comprising T4 DPLL and T4 Output APLL. The T0 path is a high quality, highly configurable path designed to provide features necessary for node timing synchronization within a SONET/SDH network. The T4 path is a simpler and less configurable path designed to give a totally independent path for internal equipment synchronization. The device supports use of either or both paths, either locked together or independent. The four SEC inputs ports are TTL/CMOS, 3 V and 5 V compatible (with clamping if required by connecting the VDD5V pin). Refer to the electrical characteristics section for more information on the electrical compatibility and details. Input frequencies supported range from 2 kHz to 100 MHz. Common E1, DS1, OC3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock to. Any input frequency, up to 100 MHz, that is a multiple of 8 kHz can also be locked to via an inbuilt programmable divider. www.semtech.com Page 7 ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET Greater programmable bandwidth from 0.1 Hz to 70 Hz in 10 steps (T4 path programmable bandwidth in 3 steps, 18, 35 and 70 Hz) Noise rejection on low frequency input Manual Holdover frequency control Controllable automatic Holdover frequency filtering Frame Sync pulse alignment. Either the software or an internal state machine controls the operation of the DPLL in the T0 path. The state machine for the T4 path is very simple and cannot be manually/externally controlled, however the overall operation can be controlled by manual reference source selection. One additional feature of the T4 path is the ability to measure a phase difference between two inputs. The T0 path DPLL always produces an output at 77.76 MHz to feed the APLL, regardless of the frequency selected at the output pins. The T4 path can be operated at a number of frequencies. This is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 MHz. When the T4 path is selected to lock to the T0 path, the T4 DPLL locks to the 8 kHz from the T0 DPLL. This is because all of the frequencies of operation of the T4 path can be divided to 8 kHz and this will ensure synchronization of all the frequencies within the two paths. Both of the DPLLs' outputs are connected to multiplying and filtering APLLs. The outputs of these APLLs are divided making a number of frequencies simultaneously available for selection at the output clock ports. The various combinations of DPLL, APLL and divider configurations allow for generation of a comprehensive set of frequencies as listed in Table 12). To synchronize the lower output frequencies when the T0 PLL is locked to a high frequency reference input, an additional input is provided. The SYNC2K pin (pin 28) is used to reset the dividers that generate the 2 kHz and 8 kHz outputs such that the output 2/8 kHz clocks are lined up with the input 2 kHz. This synchronization method could allow for example, a master and a slave device to be in precise alignment. The ACS8522 also supports Sync pulse references of 4 kHz or 8 kHz although in these cases frequencies lower than the Sync pulse reference may not necessarily be in phase. Page 8 www.semtech.com An input reference monitor is assigned to each of the four inputs. The monitors operate continuously such that at all times the status of all of the inputs to the device are known. Each input can be monitored for both frequency and activity, activity alone, or the monitors can be disabled. The frequency monitors have a "hard" (rejection) alarm limit and a "soft" (flag only) alarm limit for monitoring frequency, whilst the reference is still within its allowed frequency band. Each input reference can be programmed with a priority number allowing references to be chosen according to the highest priority valid input. The two paths (T0 and T4) have independent priorities to allow completely independent operation of the two paths. Both paths operate either automatic or external source selection. For automatic input reference selection, the T0 path has a more complex state machine than the T4 path. The T0 and T4 PLL paths support the following common features: Automatic source selection according to input priorities and quality level Different quality levels (activity alarm thresholds) for each input Variable bandwidth, lock range and damping factor Direct PLL locking to common SONET/SDH input frequencies or any integer multiple of 8 kHz up to 100 MHz Automatic mode switching between Free-run, Locked and Holdover states Fast detection on input failure and entry into Holdover mode (holds at the last good frequency value) Frequency translation between input and output rates via direct digital synthesis High accuracy digital architecture for stable PLL dynamics combined with an APLL for low jitter final output clocks. There are a number of features supported by the T0 path that are not supported by the T4 path, although these can also all be externally controlled by software. The additional T0 features supported are: Non-revertive mode Phase Build-out on source switch (hit-less source switching) I/O phase offset control Revision 5/November 2006 (c) Semtech Corp. ACS8522 SETS LITE ADVANCED COMMUNICATIONS Input Reference Clock Ports FINAL Locking Frequency Modes There are three locking frequency modes that can be configured: Direct Lock, Lock 8k and DivN. Direct Lock Mode DATASHEET Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pinselectable (using either the SONSDHB pin or via software). Specific frequencies and priorities are set by configuration. The input ports are fully interchangeable. SDH and SONET networks use different default frequencies; the network type is selectable using cnfg_input_mode Reg. 34, Bit 2 ip_sonsdhb. For SONET, ip_sonsdhb = 1 For SDH, ip_sonsdhb = 0 On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 64). Specific frequencies and priorities are set by configuration. The frequency selection is programmed via the cnfg_ref_source_frequency register (Reg. 22, 23, 27 and 28). In Direct Lock Mode, the internal DPLL can lock to the selected input at the spot frequency of the input, for example 19.44 MHz performs the DPLL phase comparisons at 19.44 MHz. In Lock8K and DivN modes an internal divider is used prior to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. Lock8K Mode Lock8K mode automatically sets the divider parameters to divide the input frequency down to 8 kHz. Lock8K can only be used on the supported spot frequencies (see Table 4 Note(i)). Lock8k mode is enabled by setting the Lock8k bit (Bit 6) in the appropriate cnfg_ref_source_frequency register location. Using lower frequencies for phase comparisons in the DPLL results in a greater tolerance to input jitter. It is possible to choose which edge of the input reference clock to lock to, by setting 8K edge polarity (Bit 2 of Reg. 03, test_register1). Table 4 Input Reference Source Selection and Priority Table Input Port SEC1 SEC2 SEC3 SEC4 Channel Number (Bin) 0011 0100 1000 1001 Input Port Technology TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS Frequencies Supported Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 2 3 4 5 Default Priority Note: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb). Revision 5/November 2006 (c) Semtech Corp. Page 9 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS DivN Mode FINAL Clock Quality Monitoring DATASHEET In DivN mode, the divider parameters are set manually by configuration (Bit 7 of the cnfg_ref_source_frequency register), but must be set so that the frequency after division is 8 kHz. The DivN function is defined as: DivN = "Divide by N+ 1", i.e. it is the dividing factor used for the division of the input frequency, and has a value of (N+1) where N is an integer from 1 to 12499 inclusive. Therefore, in DivN mode the input frequency can be divided by any integer value between 2 to 12500. Consequently, any input frequency which is a multiple of 8 kHz, between 8 kHz to 100 MHz, can be supported by using DivN mode. Note...Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. However only one value of N is allowed, so all inputs with DivN selected must be running at the same frequency. DivN Examples Clock quality is monitored and used to modify the priority tables. The following parameters are monitored: 1. Activity (toggling). 2. Frequency (this monitoring is only performed when there is no irregular operation of the clock or loss of clock condition). Any reference source that suffers a loss-of-activity or clock-out-of-band condition will be declared as unavailable. Clock quality monitoring is a continuous process which is used to identify clock problems. There is a difference in dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. Anomalies detected by the activity detector are integrated in a Leaky Bucket Accumulator. Occasional anomalies do not cause the Accumulator to cross the alarm setting threshold, so the selected reference source is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected. Anomalies on the currently locked-to input reference clock, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behavior. Anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required by the phase locked loop requires an alternative mechanism. The phase locked loop itself contains a fast activity detector such that within approximately two missing input clock cycles, a no-activity flag is raised and the DPLL is frozen in Holdover mode. This flag can also be read as the main_ref_failed bit (from Reg. 06, Bit 6) and can be set to indicate a phase lost state by enabling Reg. 73, Bit 6. With the DPLL in Holdover mode it is isolated from further disturbances. If the input becomes available again before the activity or frequency monitor rejection alarms have www.semtech.com (a) To lock to 2.000 MHz: (i) Set the cnfg_ref_source_frequency register to 10XX0000 (binary) to enable DivN, and set the frequency to 8 kHz - the frequency required after division. (XX = "Leaky Bucket" ID for this input). (ii) To achieve 8 kHz, the 2 MHz input must be divided by 250. So, if DivN = 250 = (N + 1) then N must be set to 249. This is done by writing F9 hex (249 decimal) to the DivN register pair Reg. 46/47. (b) To lock to 10.000 MHz: (i) The cnfg_ref_source_frequency register is set to 10XX0000 (binary) to set the DivN and the frequency to 8 kHz, the post-division frequency. (XX = "Leaky Bucket" ID for this input). (ii) To achieve 8 kHz, the 10 MHz input must be divided by 1,250. So, if DivN, = 250 = (N+1) then N must be set to 1,249. This is done by writing 4E1 hex (1,249 decimal) to the DivN register pair Reg. 46/47 Revision 5/November 2006 (c) Semtech Corp. Page 10 ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET been raised, then the DPLL will continue to lock to the input, with little disturbance. In this scenario, with the DPLL in the "locked" state, the DPLL uses "nearest edge locking" mode (180 capture) avoiding cycle slips or glitches caused by trying to lock to an edge 360 away, as would happen with traditional PLLs. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the Accumulator is incremented. The Accumulator will continue to increment up to the point that it reaches the programmed Bucket size. The "fill rate" of the Leaky Bucket is, therefore, 8 units/second. The "leak rate" of the Leaky Bucket is programmable to be in multiples of the fill rate (x 1, x 0.5, x 0.25 and x 0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to "leak" at the same time as a "fill" is avoided by preventing a leak when a fill event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out-of-band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, qualified reference source is selected. Interrupts for Activity Monitors Activity Monitoring The ACS8522 has a combined inactivity and irregularity monitor. The ACS8522 uses a Leaky Bucket Accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. On the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur further apart, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 3. There is one Leaky Bucket Accumulator per input channel. Each Leaky Bucket can select from four Configurations (Leaky Bucket Configuration 0 to 3). Each Leaky Bucket Configuration is programmable for size, alarm set and reset thresholds, and decay rate. The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt, if not masked. The time taken to raise this interrupt is dependent on the Leaky Bucket Configuration of the activity monitors. The fastest Leaky Bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the main_ref_failed interrupt (Reg. 06 Bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to Reg. 48 Bit 6. Revision 5/November 2006 (c) Semtech Corp. Page 11 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 3 Inactivity and Irregularity Monitoring Inactivities/Irregularities FINAL DATASHEET Reference Source bucket_size Leaky Bucket Response Programmable Fall Slopes upper_threshold lower_threshold (all programmable) Alarm Leaky Bucket Timing The time taken (in seconds) to raise an inactivity alarm on a reference source that has previously been fully active (Leaky Bucket empty) will be: (cnfg_upper_threshold_n) / 8 where n is the number of the Leaky Bucket Configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_upper_threshold is 6, therefore the default time is 0.75 s. The time taken (in seconds) to cancel the activity alarm on a previously completely inactive reference source is calculated, for a particular Leaky Bucket, as: [2 (a) x (b - c)]/ 8 where: a = cnfg_decay_rate_n b = cnfg_bucket_size_n c = cnfg_lower_threshold_n (where n = the number of the relevant Leaky Bucket Configuration in each case). The default setting is shown in the following: [21 x (8 - 4)] /8 = 1.0 secs The sts_reference_sources out-of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. With the default register settings a soft alarm is raised if the drift is outside 11.43 ppm and a hard alarm is raised if the drift is outside 15.24 ppm. Both of these limits are programmable from 3.8 ppm up to 61 ppm. The ACS8522 DPLL has a programmable lock and capture range frequency limit up to 80 ppm (default is 9.2 ppm). Selection of Input Reference Clock Source Under normal operation, the input reference sources are selected automatically by an order of priority. But, for special circumstances, such as chip or board testing, the selection may be forced by configuration. Automatic operation selects a reference source based on its pre-defined priority and its current availability. A table is maintained which lists all reference sources in the order of priority. This is initially defined by the default configuration and can be changed via the Serial interface by the Network Manager. In this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. For this, the ACS8522 has two modes of operation; Revertive and Non-revertive. www.semtech.com Frequency Monitoring The ACS8522 performs input frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range measured with respect either to the output clock or to the XO clock. Revision 5/November 2006 (c) Semtech Corp. Page 12 ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET In Revertive mode, if a re-validated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. Many applications prefer to minimize the clock switching events and choose Non-revertive mode. In Non-revertive mode, when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. The re-validation of the reference source will be flagged in the sts_sources_valid register (Reg. 0E and 0F) and, if not masked, will generate an interrupt. Selection of the re-validated source can take place under software control or if the currently selected source fails. To enable software control, the software should briefly enable Revertive mode to effect a switch-over to the higher priority source. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-revertive mode remains on, and the currently selected source is valid. A failure of the selected reference will always trigger a switch-over regardless of whether Revertive or Non-revertive mode has been chosen. by Table 4. The selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. Each reference source should be given a unique number; the valid values are 1 to 15 (dec). A value of zero disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. Revertive/Non-revertive mode has no effect on sources with the same priority value. Ultra Fast Switching A reference source is normally disqualified after the Leaky Bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if Reg. 48 Bit 5 (ultra_fast_switch) is set, then a loss of activity of just a few reference clock cycles will set the main_ref_failed alarm and cause a reference switch. This can be configured (see Reg. 06, Bit 6) to cause an interrupt to occur instead of, or as well as, causing the reference switch. The sts_interrupts register Reg. 06 Bit 6 (main_ref_failed) is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If Reg. 48 Bit 6 of the cnfg_monitors register (los_flag_on_TDO) is set, then the state of this bit is driven onto the TDO pin of the device. Note...The flagging of the loss of the main reference failure on TDO is simply allowing the status of the sts_interrupts bit main_ref_failed (Reg. 06, Bit 6) to be reflected in the state of the TDO output pin. The pin will, therefore, remain High until the interrupt is cleared. This functionality is not enabled by default so the usual JTAG functions can be used. When the TDO output from the ACS8522 is connected to the TDI pin of the next device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. Forced Control Selection A configuration register, force_select_reference_source Reg. 33, controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). For Automatic choice of source selection, the four LSB bit value is set to all zeros or all ones (default). To force a particular input the bit value must be set as follows: 0011 forces SEC1, 0100 forces SEC2, 1000 forces SEC3 and 1001 forces SEC4. Forced selection is not the normal mode of operation, and the force_select_reference_source variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. Automatic Control Selection When an automatic selection is required, the force_select_reference_source register LSB four bits must be set to all zeros or all ones. The configuration registers, cnfg_ref_selection_priority (Reg. 19, 1B and 1C), hold 4-bit values which represents the desired priority of that particular port. Unused ports should be given the value 0000 in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined Revision 5/November 2006 (c) Semtech Corp. Fast External Switching Mode-SRCSW pin Fast External Switching mode allows fast switching between inputs SEC1 and SEC2 only. The mode must first be enabled before switching can take place, and then switching is controlled via the SRCSW pin. www.semtech.com Page 13 ACS8522 SETS LITE ADVANCED COMMUNICATIONS There are two ways to enable Fast External Switching mode: Mode enable by register write - by writing to Reg. 48 Bit 4, or Mode enable by hardware "initialization" - by holding SRCSW High throughout reset and for at least a further 251 ms after PORB has gone High (250 ms allowance for the internal reset to be removed plus 1 ms allowance for APLLs to start-up and become stable). A simple external circuit to set SCRSW high for the required period is shown in "Simplified Application Schematic" on page 114. If SCRSW pin is held Low at any time during the 251 ms initialization period, this may result in Fast External Switching mode not being enabled correctly. Once Fast External Switching mode is enabled, then the value of the SRCSW pin directly selects either SEC1 (SRCSW High) or SEC2 (SRCSW Low). If this mode is enabled by hardware initialization, then it configures the default frequency tolerance of SEC1 and SEC2 to 80 ppm (Reg. 41 and Reg. 42). Either of these registers can be subsequently reconfigured by external software, if required. When Fast External Switching mode is enabled, the device operates as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock on to the indicated reference source. Consequently the device will always indicate "locked" state in the sts_operating register (Reg. 09, Bits 2:0). FINAL DATASHEET completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run Mode The Free-run mode is typically used following a power-onreset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8522 are based on the 12.800 MHz clock frequency provided from the external oscillator and are not synchronized to an input reference source. By default, the frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the oscillator. However the external oscillator frequency can be calibrated to improve its accuracy by a software calibration routine using register cnfg_nominal_frequency (Reg. 3C and 3D). For example a 500 ppm offset crystal could be made to look like one accurate to within 0.02 ppm. The transition from Free-run to Pre-locked occurs when the ACS8522 selects a reference source. Pre-locked Mode The ACS8522 will enter the Locked state in a maximum of 100 seconds, as defined by GR-1244-CORE[19] specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected. Output Clock Phase Continuity on Source Switchover If either PBO is selected on (default), or, if DPLL frequency limit is set to less than 30 ppm or (9.2 ppm default), the device will always comply with GR-1244-CORE[19] specification for Stratum 3 (maximum rate of phase change of 81 ns/1.326 ms), for all input frequencies. Locked Mode The Locked mode is entered from Pre-locked, Pre-locked2 or Phase-lost mode when an input reference source has been selected and the DPLL has locked. The DPLL is considered to be locked when the phase loss/lock detectors (See"Phase Lock/Loss Detection" on page 19) indicate that the DPLL has remained in phase lock continuously for at least one second. When the ACS8530 is in Locked mode, the output frequency and phase tracks that of the selected input reference source. Modes of Operation The ACS8522 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-locked, Lost-phase and Pre-locked2). These are shown in the State Transition Diagram, Figure 4. The ACS8522 can operate in Forced or Automatic control. On reset, the ACS8522 reverts to Automatic Control, where transitions between states are controlled Revision 5/November 2006 (c) Semtech Corp. Lost-phase Mode Lost-phase mode is used whenever the phase loss/lock detectors (See"Phase Lock/Loss Detection" on page 19) www.semtech.com Page 14 ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET Fast - (Reg. 40 Bit 6, cnfg_holdover_modes, fast_averaging: set High), giving a -3 dB filter response point corresponding to a period of approximately eight minutes, or Slow - (Reg. 40 Bit 6, cnfg_holdover_modes, fast_averaging: set Low) giving a -3 dB filter response point corresponding to a period of approximately 110 minutes. Instantaneous indicate that the DPLL has lost phase lock. The DPLL will still be trying to lock to the input clock reference, if it exists. If the Leaky Bucket Accumulator calculates that the anomaly is serious, the device disqualifies the reference source. If the device spends more than 100 seconds in Lost-phase mode, the reference is disqualified and a phase alarm is raised on it. If the reference is disqualified, one of the following transitions takes place: 1. Go to Pre-locked2; - If a known good stand-by source is available. 2. Go to Holdover; - If no stand-by sources are available. Holdover Mode Holdover mode is the operating condition the device enters when its currently selected input source becomes invalid, and no other valid replacement source is available. In this mode, the device resorts to using stored frequency data, acquired when the input reference source was still valid, to control its output frequency. In Holdover mode, the ACS8522 provides the timing and synchronization signals to maintain the Network Element but is not phase locked to any input reference source. Its output frequency is determined by an averaged version of the DPLL frequency when last in the Locked Mode. Holdover can be configured to operate in either: Automatic mode (Reg. 34 Bit 4, cnfg_input_mode: man_holdover set Low), or Manual mode (Reg. 34 Bit 4, cnfg_input_mode: man_holdover set High). Automatic Mode In Instantaneous mode, the DPLL freezes at the frequency it was operating at the time of entering Holdover mode. It does this by using only its internal DPLL integral path value (as reported in Reg. 0C, 0D, and 07) to determine output frequency. The DPLL proportional path is not used so that any recent phase disturbances have a minimal effect on the Holdover frequency. The integral value used can be viewed as a filtered version of the locked output frequency over a short period of time. The period being in inverse proportion to the DPLL bandwidth setting. Manual Mode In Automatic mode, the device can be configured to operate using either: Averaged - (Reg. 40 Bit 7, cnfg_holdover_modes, auto_averaging: set High), or Instantaneous - (Reg. 40 Bit 7, cnfg_holdover_modes, auto_averaging: set Low). Averaged (Reg. 34 Bit 4, cnfg_input_mode, man_holdover set High.) The Holdover frequency is determined by the value in register cnfg_holdover_frequency (Reg. 3E, Reg. 3F, and part of Reg. 40). This is a 19-bit signed number, with a LSB resolution of 0.0003068 ppm, which gives an adjustment range of 80 ppm. This value can be derived from a reading of the register sts_current_DPLL_frequency (Reg. 0D, 0C and 07), which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. If required, this value could be read by external software and averaged over time. The averaged value could then be fed to the cnfg_holdover_frequency register, ready for setting the averaged frequency value when the device enters Holdover mode. The sts_current_DPLL_frequency value is internally derived from the Digital Phase Locked Loop (DPLL) integral path, which represents a short-term average measure of the current frequency, depending on the locked loop bandwidth (Reg. 67) selected. It is also possible to combine the internal averaging filters with some additional software filtering. For example the internal fast filter could be used as an anti-aliasing filter and the software could further filter this before determining the actual Holdover frequency. To support this feature, a facility to read out the internally averaged frequency has been provided. www.semtech.com In the Averaged mode, the frequency (as reported by sts_current_DPLL_frequency, see Reg. 0C, Reg. 0D and Reg. 07) is filtered internally using an Infinite Impulse Response filter, which can be set to either: Revision 5/November 2006 (c) Semtech Corp. Page 15 ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 4 Automatic Mode Control State Diagram FINAL DATASHEET (1) Reset Free-run select ref (state 001) (3) no valid standby ref & (main ref invalid or out of lock > 100s (2) all refs evaluated & at least one ref valid Reference sources are flagged as valid when active, in-band and have no phase alarm set. (4) valid standby ref & [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock > 100s] Pre-locked wait for up to 100s (state 110) All sources are continuously checked for activity and frequency Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds. (5) selected ref phase locked Locked keep ref (state 100) (10) selected source phase locked (8) phase regained (9) valid standby ref within 100s & [main ref invalid or (higher priority ref valid & in revertive mode)] (12) valid standby ref & (main ref invalid or out of lock >100s) (6) no valid standby ref & main ref invalid (7) phase lost on main ref Pre-locked2 wait for up to 100s (state 101) Lost-phase wait for up to 100s (state 111) (11) no valid standby ref & (main ref invalid or out of lock >100s) Holdover select ref (state 010) (15) valid standby ref & [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid F8530D_018AutoModeContStateDia_02 Revision 5/November 2006 (c) Semtech Corp. Page 16 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET By setting Reg. 40, Bit 5, cnfg_holdover_modes, read_average, the value read back from the cnfg_holdover_frequency register will be the filtered value. The filtered value is available regardless of what actual Holdover mode is selected. Clearly this results in the register not reading back the data that was written to it. Example: Software averaging to eliminate temperature drift. instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature fluctuations are). It is advantageous to shield the TCXO/OCXO to slow down frequency changes due to drift and external temperature fluctuations. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator. Select Manual Holdover mode by setting Reg. 34 Bit 4, cnfg_input_mode, man_holdover High. Select Fast Holdover Averaging mode by setting Reg. 40 Bit 6, cnfg_holdover_modes, auto_averaging High and Reg. 40 Bit 7 High. Select to be able to read back filtered output by setting Reg. 40 Bit 5, cnfg_holdover_modes, read_average High. Software periodically reads averaged value from the cnfg_holdover_frequency register and the temperature (not supplied from ACS8522). Software processed frequency and temperature and places data in software look-up table or other algorithm. Software writes back appropriate averaged value into the cnfg_holdover_frequency register. Once Holdover mode is entered, software periodically updates the cnfg_holdover_frequency register using the temperature information (not supplied from ACS8522). Mini-holdover Mode Pre-locked2 Mode This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. Upon applying a reference source to the phase locked loop, the ACS8522 will enter the Locked state in a maximum of 100 seconds, as defined by GR-1244CORE[19] specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Holdover mode and another reference source is selected. Holdover mode so far described refers to a state to which the internal state machine switches as a result of activity or frequency alarms, and this state is reported in Reg. 09. To avoid the DPLL's frequency being pulled off as a result of a failed input, then the DPLL has a fast mechanism to freeze its current frequency within one or two cycles of the input clock source stopping. Under these circumstances the DPLL enters Mini-holdover mode; the Mini-holdover frequency used being determined by Reg. 40, Bits [4:3], cnfg_holdover_modes, mini_holdover_mode. Mini-holdover mode only lasts until one of the following happens: A new source has been selected, or The state machine enters Holdover mode, or The original fault on the input recovers. External Factors Affecting Holdover Mode DPLL Architecture and Configuration A Digital PLL gives a stable and consistent level of performance that can be easily programmed for different dynamic behavior or operating range. It is not affected by operating conditions or silicon process variations. Digital synthesis is used to generate all required SONET/SDH output frequencies. The digital logic operates at 204.8 MHz that is multiplied up from the external 12.800 MHz oscillator module. Hence the best resolution of the output signals from the DPLL is one 204.8 MHz cycle or 4.9 ns. Additional resolution and lower final output jitter is provided by a de-jittering Analog PLL that reduces the 4.9 ns pk-pk jitter from the digital down to 500 ps pk-pk and 60 ps RMS as typical final outputs measured broadband (from 10 Hz to 1 GHz). This arrangement combines the advantages of the flexibility and repeatability of a DPLL with the low jitter of an APLL. The DPLLs in the ACS8522 are uniquely very If the external TCXO/OCXO frequency is varying due to temperature fluctuations in the room, then the Revision 5/November 2006 (c) Semtech Corp. Page 17 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL T4 DPLL Main Features Single programmable DPLL bandwidth control: 18 Hz, 35 Hz or 70 Hz Programmable damping factor: For optional faster locking and peaking control. Factors = 1.2, 2.5, 5, 10 or 20 Multiple phase lock detectors Multi-cycle phase detection and locking, programmable up to 8192 UI - improves jitter tolerance in direct lock mode DS3/E3 support (44.736 MHz / 34.368 MHz) at same time as OC-N rates from T0 DPLL Low jitter E1/DS1 options at same time as OC-N rates from T0 DPLL Frequencies of n x E1/DS1 including 16 and 12 x E1, and 16 and 24 x DS1 supported Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs Can use the T4 DPLL as an Independent FrSync DPLL Can use the phase detector in T4 DPLL to measure the input phase difference between two inputs. The structure of the T0 and T4 PLLs are shown later in Figure 10 in the section on output clock ports. That section also details how the DPLLs and particular output frequencies are configured. The following sections detail some component parts of the DPLL. DATASHEET programmable for all PLL parameters of bandwidth (from 0.1 Hz up to 70 Hz), damping factor (from 1.2 to 20), frequency acceptance and output range (from 0 to 80 ppm, typically 9.2 ppm), input frequency (12 common SONET/SDH spot frequencies) and input-to-output phase offset (in 6 ps steps up to 200 ns). There is no requirement to understand the loop filter equations or detailed gain parameters since all high level factors such as overall bandwidth can be set directly via registers in the microprocessor interface. No external critical components are required for either the internal DPLLs or APLLs, providing another key advantage over traditional discrete designs. The T4 DPLL is similar in structure to the T0 DPLL, but since the T4 is only providing a clock synthesis and input to output frequency translation function, with no defined requirement for jitter attenuation or input phase jump absorption, then its bandwidth is limited to the high end and the T4 does not incorporate many of the Phase Buildout and adjustment facilities of the T0 DPLL. TO DPLL Main Features Two programmable DPLL bandwidth controls (Locked and Acquisition bandwidth), each with 10 steps from 0.1 Hz to 70 Hz Programmable damping factor: For optional faster locking and peaking control. Factors = 1.2, 2.5, 5, 10 or 20 Multiple phase lock detectors Input to output phase offset adjustment (Master/Slave), 200 ns, 6 ps resolution step size PBO phase offset on source switching - disturbance down to 5 ns Multi-cycle phase detection and locking, programmable up to 8192 UI - improves jitter tolerance in direct lock mode Holdover frequency averaging with a choice of: Average times: 8 minutes or 110 minutes. Value can also be read out. Multiple E1 and DS1 outputs supported Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs. Revision 5/November 2006 (c) Semtech Corp. TO DPLL Automatic Bandwidth Controls In Automatic Bandwidth Selection mode (Reg. 3B), the T0 DPLL bandwidth setting is selected automatically from the Acquisition Bandwidth or Locked Bandwidth configurations programmed in cnfg_T0_DPLL_acq_bw Reg. 69 and cnfg_T0_DPLL_locked_bw Reg. 67 respectively. If this mode is not selected, the DPLL acquires and locks using only the bandwidth set by Reg. 67. Phase Detectors A Phase and Frequency detector is used to compare input and feedback clocks. This operates at input frequencies up to 77.76 MHz. The whole DPLL can operate at spot frequencies from 2 kHz up to 77.76 MHz. A common arrangement however is to use Lock8k mode (see Bit 6 of Reg. 22, 23, 27 and 28) where all input frequencies are divided down to 8 kHz internally. Marginally better MTIE figures may be possible in direct lock mode due to more regular phase updates. www.semtech.com Page 18 ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET A patented multi-phase detector is used in order to give an infinitesimally small input phase resolution combined with large jitter tolerance. The following phase detectors are used: Phase and frequency detector (360 or 180 range) An early/late phase detector for fine resolution A multi-cycle phase detector for large input jitter tolerance (up to 8191 UI), which captures and remembers phase differences of many cycles between input and feedback clocks. The phase detectors can be configured to be immune to occasional missing input clock pulses by using nearest edge detection (180 capture) or the normal 360 phase capture range which gives frequency locking. The device will automatically switch to nearest edge locking when the multi-UI phase detector is not enabled and the other phase detectors have detected that phase lock has been achieved. It is possible to disable the selection of nearest edge locking via Reg. 03 Bit 6 set to 1. In this setting, frequency locking will always be enabled. The balance between the first two types of phase detector employed can be adjusted via registers 6A to6D. The default settings should be sufficient for all modes. Adjustment of these settings affects only small signal overshoot and bandwidth. The multi-cycle phase detector is enabled via Reg. 74, Bit 6 set to 1 and the range is set in exponentially increasing steps from 1 UI, 3 UI, 7 UI, 15 UI ... up to 8191 UI via Reg. 74, Bits [3:0]. When this detector is enabled it keeps a track of the correct phase position over many cycles of phase difference to give excellent jitter tolerance. This provides an alternative to switching to Lock8k mode as a method of achieving high jitter tolerance. An additional control (Reg. 74 Bit 5) enables the multiphase detector value to be used in the final phase value as part of the DPLL loop. When enabled by setting High, the multi cycle phase value will be used in the loop and gives faster pull in (but more overshoot). The characteristics of the loop will be similar to Lock8k mode where again large input phase differences contribute to the loop dynamics. Setting the bit Low only uses a max figure of 360 degrees in the loop and will give slower pullin but gives less overshoot. The final phase position that Revision 5/November 2006 (c) Semtech Corp. the loop has to pull in to is still tracked and remembered by the multi-cycle phase detector in either case. Phase Lock/Loss Detection Phase lock/loss detection is handled in several ways. Phase loss can be triggered from: The fine phase lock detector, which measures the phase between input and feedback clock The coarse phase lock detector, which monitors whole cycle slips Detection that the DPLL is at min. or max. frequency Detection of no activity on the input. Each of these sources of phase loss indication is individually enabled via register bits (see Reg. 73, 74 and 4D). Phase lock or lost is used to determine whether to switch to nearest edge locking and whether to use acquisition or Locked bandwidth settings for the DPLL. Acquisition bandwidth is used for faster pull-in from an unlocked state. The coarse phase lock detector detects phase differences of n cycles between input and feedback clocks, where n is set by Reg. 74, Bits 3:0; the same register that is used for the coarse phase detector range, since these functions go hand in hand. This detector may be used in the case where it is required that a phase loss indication is not given for reasonable amounts of input jitter and so the fine phase loss detector is disabled and the coarse detector is used instead. Damping Factor Programmability The DPLL damping factor is set by default to provide a maximum wander gain peak of around 0.1 dB. Many of the specifications (e.g. GR-1244-CORE[19], G.812[10] and G.813[11]) specify a wander transfer gain of less than 0.2 dB. GR-253[17] specifies jitter (not wander) transfer of less than 0.1 dB. To accommodate the required levels of transfer gain, the ACS8522 provides a choice of damping factors, with more choice given as the bandwidth setting increases into the frequency regions classified as jitter. Table 5 shows which damping factors are available for selection at the different bandwidth settings, and what the corresponding jitter transfer approximate gain peak will be. Page 19 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL Parameter Tolerance Drift (Frequency Drift over supply voltage range of +2.7 V to +3.3 V) Value 4.6 ppm over 20 year lifetime 0.05 ppm/15 seconds @ constant temp. 0.04 ppm/15 seconds @ constant temp. 0.28 ppm/over temp. range 0 to +50C DATASHEET Table 5 Available Damping Factors for different DPLL Bandwidths, and associated Jitter Peak Values Bandwidth 0.1 Hz to 4 Hz 8 Hz Reg. 6B [2:0] 1, 2, 3, 4, 5 1 2, 3, 4, 5 18 Hz 1 2 3, 4, 5 35 Hz 1 2 3 4, 5 70 Hz 1 2 3 4 5 Damping Gain Peak/ dB Factor selected 5 2.5 5 1.2 2.5 5 1.2 2.5 5 10 1.2 2.5 5 10 20 0.1 0.2 0.1 0.4 0.2 0.1 0.4 0.2 0.1 0.06 0.4 0.2 0.1 0.06 0.03 Table 7 Telcordia GR-1244 CORE Specification and a drift of 280 ppb over the temperature range 0 to +50C. Please contact Semtech for information on crystal oscillator suppliers Crystal Frequency Calibration Local Oscillator Clock The Master system clock on the ACS8522 should be provided by an external clock oscillator of frequency 12.800 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperature-related parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70C. Table 6 ITU and ETSI Specification Parameter Tolerance Drift (Frequency Drift over supply voltage range of +2.7 V to +3.3 V) Value 4.6 ppm over 20 year lifetime 0.05 ppm/15 seconds @ constant temp. 0.01 ppm/day @ constant temp. 1 ppm over temp. range 0 to +70C The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8-bit register locations. The setting of the cnfg_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.0196229 ppm for each LSB step. Note...The default register value (in decimal) = 39321 (9999 hex) = 0 ppm offset. The minimum to maximum offset range of the register is 0 to 65535 dec, giving an adjustment range of -771 ppm to +514 ppm of the output frequencies, in 0.0196229 ppm steps. Example: If the crystal was oscillating at 12.800 MHz + 5 ppm, then the calibration value in the register to give a - 5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be: 39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex). Output Wander Wander and jitter present on the output clocks are dependent on: The magnitudes of wander and jitter on the selected input reference clock (in Locked mode) The internal wander and jitter transfer characteristic (in Locked mode) The jitter on the local oscillator clock The wander on the local oscillator clock (in Holdover mode). Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always www.semtech.com Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day Revision 5/November 2006 (c) Semtech Corp. Page 20 ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state. Wander and jitter attenuation is performed using a digital phase locked loop (DPLL) with a programmable bandwidth. This gives a transfer characteristic of a low pass filter, with a programmable pole. It is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, the filter can be opened up to reduce locking time and can then be tightened again to remove wander. A change between different bandwidths for locking and for acquisition is handled automatically within the ACS8522. There may be a phase shift across the ACS8522 between the selected input reference source and the output clock over time, mainly caused by frequency wander in the external oscillator module. Higher stability XOs will give better performance for MTIE. The oscillator becomes more critical at DPLL bandwidth near to or below 0.1 Hz since the rate of change of the DPLL may be slow compared to the rate of change of the oscillator frequency. Shielding of the OCXO or TCXO can further slow down the rate of change of temperature and hence frequency, thus improving output wander performance. The phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterized using two parameters, MTIE (Maximum Time Interval Error) and TDEV (Time Deviation) which, although being specified in all relevant specifications, differ in acceptable limits in each one. Typical measurements for the ACS8522 are shown in Figure 5, for Locked mode operation. Figure 6 shows a typical measurement of Phase Error accumulation in Holdover mode operation. The required performance for phase variation during Holdover is specified in several ways and depends on the relevant specification (See "References" on page 115), for example: 1. ETSI ETS-300 462-5[4], Section 9.1, requires that the short-term phase error during switchover (i.e. Locked to Holdover to Locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. 2. ETSI ETS-300 462-5[4], Section 9.2, requires that the long-term phase error in the Holdover mode should not exceed: {(a1 + a2)S + 0.5bS2 + c} where a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16x10-4 ns/s2 (allowance for ageing) c = 120 ns (allowance for entry into Holdover mode). S = Elapsed time (s) after loss of external ref. input 3. ANSI Tin1.101-1999[1], Section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 s each) occur during the first day of Holdover. This requires a frequency accuracy better than: ((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm Temperature variation is not restricted, except to within the normal bounds of 0 to 50C. 4. Telcordia GR-1244-CORE[19], Section 5.2, shows that an initial frequency offset of 50 ppb is permitted on entering Holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. 5. ITU G.822[12], Section 2.6, requires that the slip rate during category (b) operation (interpreted as being applicable to Holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour. ((60 x 60) + (30 x 125 s))/(60 x 60)) = 1.042 ppm Revision 5/November 2006 (c) Semtech Corp. Page 21 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 5 Maximum Time Interval Error and Time Deviation of T0 PLL Output Port MTIE for G.813 option 1, Constant temperature wander limit TDEV for G.813 option 1, Constant temperature wander limit F8530D_027MtieTdevCombF6_01 Figure 6 Phase Error Accumulation of T0 PLL Output Port in Holdover Mode 10000000 1000000 Phase Error (ns) Permitted Phase Error Limit 100000 10000 Typical measurement, 25C constant temperature 1000 100 1000 10000 100000 Observation interval (s) Revision 5/November 2006 (c) Semtech Corp. Page 22 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Jitter and Wander Transfer The ACS8522 has a programmable jitter and wander transfer characteristic. This is set by the DPLL bandwidth. The -3 dB jitter transfer attenuation point can be set in the range from 0.1 Hz to 70 Hz in 10 steps. The wander and jitter transfer characteristic is shown in Figure 7. Wander on the local oscillator clock will not have a significant effect on the output clock whilst in Locked mode, provided that the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-run or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section See Local Oscillator Clock. FINAL states that the maximum allowable shortITU-T G.813 term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. The ACS8522 performance is well within this requirement. The typical phase disturbance on clock reference source switching will be less than 5 ns on the ACS8522. When a PBO event is triggered, the device enters a temporary Holdover state. When in this temporary state, the phase of the input reference is measured, relative to the output. The device then automatically accounts for any measured phase difference and adds the appropriate phase offset into the DPLL to compensate. Following a PBO event, whatever the phase difference on change of input, the output phase transient is minimized to be no greater than 5 ns. On the ACS8522, PBO can be enabled, disabled or frozen using the serial interface. By default, it is enabled. When PBO is enabled, PBO can also be frozen (at the current offset setting). The device will then ignore any further PBO events occurring on any subsequent reference switch, and maintain the current phase offset. If PBO is disabled [11] DATASHEET Phase Build-out Phase Build-out (PBO) is the function to minimize phase transients on the output SEC clock during input reference switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference) the second, next highest priority reference source will be selected, and a PBO event triggered. Figure 7 Sample of Wander and Jitter Measured Transfer Characteristics Revision 5/November 2006 (c) Semtech Corp. Page 23 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL Input Wander and Jitter Tolerance The ACS8522 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825[15], ANSI DS1.101-1999[1], Telcordia GR1244[19], GR253[17], G812[10], G813[11] and ETS 300 462-5 (1996)[4]. All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pull-in, hold-in and pull-out ranges are specified in Table 8. Minimum jitter tolerance masks are specified in Figures 8 and 9, and Tables 8 and 10, respectively. The ACS8522 will tolerate wander and jitter components greater than those shown in Figure 8 and Figure 9, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). Either the Lock8k mode, or one of the extended phase capture ranges should be engaged for high jitter tolerance according to these masks. All reference clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause re- arrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. DATASHEET while the device is in the Locked mode, there may be a phase shift on the output SEC clocks as the DPLL locks back to 0 degrees phase error. The rate of phase shift will depend on the programmed bandwidth. Enabling PBO whilst in the Locked stated will also trigger a PBO event. PBO Phase Offset In order to minimize the systematic (average) phase error for PBO, a PBO Phase Offset can be programmed in 0.101 ns steps in the cnfg_PBO_phase_offset register, Reg.72. The range of the programmable PBO phase offset is restricted to 1.4 ns. This can be used to eliminate an accumulation of phase shifts in one direction. Input-to-Output Phase Adjustment When PBO is off (including Auto-PBO on phase transients), such that the system always tries to align the outputs to the inputs at the 0 position, there is a mechanism provided in the ACS8522 for precise fine tuning of the output phase position with respect to the input. This can be used to compensate for circuit and board wiring delays. The output phase can be adjusted in 6 ps steps up to 200 ns in a positive or negative direction. The phase adjustment actually changes the phase position of the feedback clock so that the DPLL adjusts the output clock phases to compensate. The rate of change of phase is therefore related to the DPLL bandwidth. For the DPLL to track large instant changes in phase, either Lock8k mode should be on, or the coarse phase detector should be enabled. Register cnfg_phase_offset at Reg. 70 and 71 controls the output phase, which is only used when PBO is off (Reg. 48, Bit 2 = 0 and Reg. 76, Bit 4 = 0). Revision 5/November 2006 (c) Semtech Corp. Page 24 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 8 Input Reference Source Jitter Tolerance Jitter Tolerance Frequency Monitor Acceptance Range Frequency Acceptance Range (Pull-in) Frequency Acceptance Range (Hold-in) Frequency Acceptance Range (Pull-out) FINAL DATASHEET G.703[6] G.783[9] G.823[13] GR-1244-CORE[19] Notes: (i) The frequency acceptance and generation range will be 4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of 4.6 ppm. (ii) The fundamental acceptance range and generation range is 9.2 ppm with an exact external crystal frequency of 12.800 MHz. This is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps. 16.6 ppm 4.6 ppm (see Note (i)) 9.2 ppm (see Note (ii)) 4.6 ppm (see Note (i)) 9.2 ppm (see Note (ii)) 4.6 ppm (see Note (i)) 9.2 ppm (see Note (ii)) Figure 8 Minimum Input Jitter Tolerance (OC-3/STM-1) A0 A1 A2 A3 A4 Jitter and Wander Frequency (log scale) f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 Note...For inputs supporting G.783[9] compliant sources.) F8530_003MINIPJITTOLOC3STM1_02 Table 9 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1) STM level Peak to peak amplitude (unit Interval) A0 STM-1 2800 A1 A2 A3 A4 F0 F1 F2 F3 Frequency (Hz) F4 F5 19.3 F6 F7 F8 F9 311 39 1.5 0.15 12 u 178 u 1.6 m 15.6 m 0.125 500 6.5 k 65 k 1.3 Revision 5/November 2006 (c) Semtech Corp. Page 25 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 9 Minimum Input Jitter Tolerance (DS1/E1) Peak-to-peak Jitter and Wander Amplitude (log scale) FINAL DATASHEET A1 A2 Jitter and Wander Frequency (log scale) f1 f2 f3 f4 F8530D_004MINIPJITTOLDS1E1_02 Table 10 Amplitude and Frequency Values for Jitter Tolerance (DS1/E1) Type Spec. Amplitude (UI pk-pk) A1 DS1 E1 GR-1244-CORE[19] ITU G.823[13] 5 1.5 0.1 0.2 A2 10 20 F1 500 2.4 k Frequency (Hz) F2 8k 18 k F3 40 k 100 F4 Using the DPLLs for Accurate Frequency and Phase Reporting The frequency monitors in the ACS8522 perform frequency monitoring with a programmable acceptable limit of up to 60.96 ppm. The resolution of the measurement is 3.8 ppm and the measured frequency can be read back from Reg. 4C, with channel selection at Reg. 4B. For more accurate measurement of both frequency and phase, the T0 and T4 DPLLs and their phase detectors, can be used to monitor both input frequency and phase. The T0 DPLL is always monitoring the currently locked to source, but if the T4 path is not used then the T4 DPLL can be used as a roving phase and frequency meter. Via software control it could be switched to monitor each input in turn and both the phase and frequency can be reported with a very fine resolution. The registers sts_current_DPLL_frequency (Reg. 0C, Reg. 0D and Reg. 07) report the frequency of either the T0 or T4 DPLL with respect to the external crystal XO frequency (after calibration via Reg. 3C, 3D if used). The selection of T4 or T0 DPLL reporting is made via Reg. 4B, Bit 4. The value is a 19-bit signed number with one LSB representing 0.0003068 ppm (range of 80 ppm). This value is actually the integral path value in the DPLL, and as such corresponds to an averaged measurement of the Revision 5/November 2006 (c) Semtech Corp. input frequency, with an averaging time inversely proportional to the DPLL bandwidth setting. Reading this regularly can show how the currently locked source is varying in value e.g. due to frequency wander on its input. The input phase, as seen at the DPLL phase detector, can be read back from register sts_current_phase, Reg. 77 and 78. T0 or T4 DPLL phase detector reporting is again controlled by Reg. 4B, Bit 4. One LSB corresponds to approximately 0.7 degrees phase difference. For the T0 DPLL this will be reporting the phase difference between the input and the internal feedback clock. The phase result is internally averaged or filtered with a -3 dB attenuation point at approximately 100 Hz. For low DPLL bandwidths, 0.1 Hz for example, this measured phase information from the T0 DPLL gives input phase wander in the frequency band from for example 0.1 Hz to 100 Hz. This could be used to give a crude input MTIE measurement up to an observation period of approximately 1000 seconds using external software. In addition, the T4 DPLL phase detector can be used to make a phase measurement between two inputs. Reg. 65, Bit 7 is used to switch one input to the T4 phase detector over to the current T0 input. The other phase detector input remains connected to the selected T4 input source, the selected source can be forced via Reg. 35, www.semtech.com Page 26 ACS8522 SETS LITE ADVANCED COMMUNICATIONS Bits 3:0, or changed via the T4 priority (Reg. 19 to 1C, when Reg. 4B, Bit 4 = 1). Consequently the phase detector from the T4 DPLL could be used to measure the phase difference between the currently selected source and the stand-by source, or it could be used to measure the phase wander of all standby sources with respect to the current source by selecting each input in sequence. An MTIE and TDEV calculation could be made for each input via external processing. FINAL DATASHEET MFrSync and 8 kHz FrSync outputs keep their precise alignment with the other output clocks. When indep_FrSync/MFrSync Reg. 7B Bit 7 is Low the FrSyncs and the other higher rate clocks are not independent and their alignment on the falling 8kHz edge is maintained. This means that when Bit Sync_OC-N_rates is High, the OC-N rate dividers and clocks are also synchronized by the SYNC2K input. On a change of phase position of the SYNC2K, this could result in a shift in phase of the 6.48 MHz output clock when a 19.44 MHz precision is used for the SYNC2K input. To avoid disturbing any of the output clocks and only align the MFrSync and FrSync outputs, at the chosen level of precision, then independent Frame Sync mode can be used (Reg. 7B, bit 7 = 1). Edge alignment of the FrSync output with other clocks outputs may then change depending on the SYNC2K sampling precision used. For example with a 19.44 MHz reference input clock and Reg. 7B, bits 6 & 7 both High (independent mode and Sync OC-N rates), then the FrSync output will still align with the 19.44 MHz output but not with the 6.48 MHz output clock. The FrSync and MFrSync outputs always come from the T0 DPLL path. 2kHz and 8kHz outputs can also be produced at the O1 to O4 outputs. These can come from either the T0 DPLL or from the T4 DPLL, controlled by Reg. 7A, bit 7. If required, this allows the T4 DPLL to be used as a separate PLL for the FrSync and MFrSync path with a 2 kHz input and 2 kHz and 8 kHz Frame Sync outputs. MFrSync and FrSync Alignment-SYNC2K The SYNC2K input will normally be a 2 kHz frequency and only its falling edge is used. It can however be at a frequencies of 4 kHz or 8 kHz without any change to the register setups. Only alignment of the 8 kHz will be achieved in this case. Safe sampling of the SYNC2K input is achieved by using the currently selected clock reference source to do the input sampling. This is based on the principle that FrSync alignment is being used on a Slave device that is locked to the clock reference of a Master device that is also providing the 2 kHz SYNC2K input. Phase Build-out mode should be off (Reg. 48, Bit 2 = 0). The 2 kHz MFrSync output from the Master device has its falling edge aligned with the falling edge of the other output clocks, hence the SYNC2K input is normally sampled on the rising edge of the current input reference clock, in order to provide the most margin. Some modification of the expected timing of the SYNC2K with respect to the reference clock can be achieved via Reg. 7B, Bits [1:0]. This allows for the SYNC2K input to arrive either half a reference clock cycle early or up to one and a half cycle late, hence allowing a safe sampling margin to be maintained. A different sampling resolution is used depending on the input reference frequency and the setting of Reg. 7B, cnfg_sync_phase, Bit 6 indep_FrSync/MFrSync. With this bit Low, the SYNC2K input sampling has a 6.48 MHz resolution, this being the preferred reference frequency to lock to from the Master, in conjunction with the SYNC2K 2 kHz, since it gives the most timing margin on the sampling and aligns all of the higher rate OC-3 derived clocks. When Bit 6 is High the SYNC2K can have a sampling resolution of either 19.44 MHz (when the current locked to reference is 19.44 MHz) or 38.88 MHz (all other frequencies). This would allow for instance a 19.44 MHz and 2 kHz pair to be used for Slave synchronization or for Line card synchronization. Reg. 7B Bit 7, indep_FrSync/MFrSync controls whether the 2 kHz Revision 5/November 2006 (c) Semtech Corp. Output Clock Ports The device supports a set of main output clocks, O1 to O4 and a pair of secondary Sync outputs, FrSync and MFrSync. The four main output clocks are independent of each other and are individually selectable. The two secondary output clocks, FrSync and MFrSync, are derived from the T0 path only. The frequencies of the main output clocks are selectable from a range of predefined spot frequencies, as defined in Table 11. Output technologies are TTL/CMOS for all outputs except O1 which can be PECL or LVDS. PECL/LVDS Output Port Selection The choice of PECL or LVDS compatibility for Output O1 is programmed via the cnfg_differential_outputs register, Reg. 3A. www.semtech.com Page 27 ACS8522 SETS LITE ADVANCED COMMUNICATIONS Output Frequency Selection and Configuration The output frequency of outputs O1 to O4 is controlled by a number of interdependent parameters. These parameters control the selections within the various blocks shown in Figure 10. The ACS8522 contains two main DPLL/APLL paths, T0 and T4. Whilst they are largely independent, there are a number of ways in which these two structures can interact. Figure 10 is an expansion of the top level Block Diagram (Figure 1) showing the PLL paths in more detail. T0 DPLL and APLLs FINAL DATASHEET DFS and the T0 77M output DFS blocks are locked in frequency but may be offset in phase. The T0 77M output DFS block also uses the 204.8 MHz system clock and always generates 77.76 MHz for the output clocks (with inherent 4.9 ns of jitter). This is fed to another DFS block and to the T0 output APLL. The low frequency T0 LF output DFS block is used to produce three frequencies; two of them, Digital1 and Digital2, are available for selection to be produced at outputs O1 to O4, and the third frequency can produce multiple E1/DS1 rates via the filtering APLLs. The input clock to the T0 LF output DFS block is either 77.76 MHz from the T0 output APLL (post jitter filtering) or 77.76 MHz direct from the T0 77M output DFS. Utilizing the clock from the T0 output APLL will result in lower jitter outputs from the T0 LF output DFS block. However, when the input to the T0 APLL is taken from the T0 LF output DFS block, the input to that block comes directly from the T0 77M output DFS block so that a "loop" is not created. The T0 output APLL is for multiplying and filtering. The input to the T0 output APLL can be either 77.76 MHz from the T0 77M output DFS block or an alternative frequency from the T0 LF output DFS block (offering 77.76 MHz, 12E1, 16E1, 24DS1 or 16DS1). The frequency from the T0 output APLL is four times its input frequency i.e. 311.04 MHz when used with a 77.76 MHz input. The T0 output APLL is subsequently divided by 1, 2, 4, 6, 8, 12, 16 and 48 and these are available at the O1 to O4 outputs. T4 DPLL & APLL The T0 DPLL always produces 77.76 MHz regardless of either the reference frequency (frequency at the input pin of the device) or the locking frequency (frequency at the input of the DPLL Phase and Frequency Detector (PFD)). The input reference is either passed directly to the PFD or via a pre-divider (not shown) to produce the reference input. The feedback 77.76 MHz is either divided or synthesized to generate the locking frequency. Digital Frequency Synthesis (DFS) is a technique for generating an output frequency using a higher frequency system clock (204.8 MHz in the case of the 77.76 MHz synthesis). However, the edges of the output clock are not ideally placed in time, since all edges of the output clock will be aligned to the active edge of the system clock. This will mean that the generated clock will inherently have jitter on it equivalent to one period of the system clock. The T0 77M forward DFS block uses DFS clocked by the 204.8 MHz system clock to synthesize the 77.76 MHz and, therefore, has an inherent 4.9 ns of pk-pk jitter. There is an option to use an APLL, the T0 feedback APLL, to filter out this jitter before the 77.76 MHz is used to generate the feedback locking frequency in the T0 feedback DFS block. This analog feedback option allows a lower jitter (<1 ns) feedback signal to give maximum performance. The digital feedback option is present so that when the output path is switched to digital feedback the two paths remain synchronized. The T0 77M forward DFS block is also the block that handles Phase Build-out and any phase offset programmed into the device. Hence, the T0 77M forward The T4 path is much simpler than the T0 path. This path offers no Phase Build-out or phase offset. The T4 input can be used to either lock to a reference clock input independent of the T0 path, or lock to the T0 path. Unlike the T0 path, the T4 forward DFS block does not always generate 77.76 MHz. The possible frequencies are listed in the table. Similar to the T0 path, the output of the T4 forward DFS block is generated using DFS clocked by the 204.8 MHz system clock and will have an inherent jitter of 4.9 ns. The T4 feedback DFS also has the facility to be able to use the post T4 APLL (jitter-filtered) clock to generate the feedback locking frequency. Again, this will give the maximum performance by using a low jitter feedback. Revision 5/November 2006 (c) Semtech Corp. Page 28 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 10 PLL Block Diagram T4 Reference Input SEC1 SEC2 SEC3 SEC4 Lock_T4_to_T0 Sts_Current_Phase Control 0 T4_DPLL_Frequency T4_APLL_for_T0 FINAL DATASHEET PFD and Loop Filter 1 T0_DPLL_Freq 0 Locking Frequency Forward DFS 0 T4_Dig_Feedback 1 1 T4 Output APLL T4 Output Dividers O1, O2 O3, O4 Feedback DFS 1 0 T4 DPLL 8 kHz T0_DPLL_Frequency Control 0 77M Output DFS Phase Offset 1 Sts_Current_Phase 0 LF Output DFS 1 T0 Output APLL T0 Output Dividers O1, O2 O3, O4 O1, O2 O3, O4 FrSync MFrSync PBO T0 Reference Input SEC1 SEC2 SEC3 SEC4 PFD and Loop Filter 77M Forward DFS 1 T0_DPLL_Frequency Control T0 Feedback APLL Locking Frequency Feedback DFS 0 T0 DPLL Analog F8522D_017BLOCKDIA_01 The T4 output APLL block is also for multiplying and filtering. The input to the T4 output APLL can come either from the T4 forward DFS block or from the T0 path. The input to the T4 output APLL can be programmed to be one of the following: (a) Output from the T4 forward DFS block (12E1, 24DS1, 16E1, 16DS1, E3, DS3, OC-N), (b) 12E1 from T0, (c) 16E1 from T0, (d) 24DS1 from T0, (e) 16DS1 from T0. The frequency generated from the T4 output APLL block is four times its input frequency i.e. 311.04 MHz when used with a 77.76 MHz input. The T4 output APLL is subsequently divided by 2, 4, 8, 12, 16, 48 and 64 and these are available at the O1 to O4 outputs. The outputs O1 to O4 are driven from either the T4 or the T0 path. The FrSync and MFrSync outputs are always generated from the T0 path. Reg.7A bit 7 selects whether the source of the 2 kHz and 8 kHz outputs available from O1 to O4 is derived from either the T0 or the T4 paths. Revision 5/November 2006 (c) Semtech Corp. Output Frequency Configuration Steps The output frequency selection is performed in the following steps: 1. Does the application require the use of the T4 path as an independent PLL path or not. If not, then the T4 path can be utilized to produce extra frequencies locked to the T0 path. 2. Refer to Table 13, Frequency Divider Look-up, to choose a set of output frequencies- one for each path, T4 and T0. Only one set of frequencies can be generated simultaneously from each path. 3. Refer to the Table 13 to determine the required APLL frequency to support the frequency set. 4. Refer to Table 14, T0 APLL Frequencies, and Table 15, T4 APLL Frequencies, to determine what mode the T0 and T4 paths need to be configured in, considering the output jitter level. 5. Refer to Table 16, O1 to O4 Output Frequency Selection, and the column headings in Table 13, Frequency Divider Look-up, to select the appropriate frequency from either of the APLLs on each output as required. www.semtech.com Page 29 ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 11 Output Reference Source Selection Table Port Name O1 O2 O3 O4 FrSync Output Port Technology LVDS/PECL (LVDS default) TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A. MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A. Frequency selection as per Table 12 and Table 16 Frequencies Supported FINAL DATASHEET MFrSync TTL/CMOS Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default, when High SONET is default. Table 12 Output Frequency Selection Frequency (MHz, unless stated otherwise) T0 DPLL Mode T4 DPLL Mode T4 APLL Input Mux Jitter Level (typ) rms (ps) 2 kHz 2 kHz 8 kHz 8 kHz 1.536 1.536 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 2.048 2.048 (not O4) (not O4) (not O1) via Digital1, or Digital2 (not O1) (not O4) (not O4) (not O4) (not O4) via Digital1, or Digital2 (not O1) via Digital1, or Digital2 (not O1) 77.76 MHz Analog Any digital feedback mode 77.76 MHz Analog Any digital feedback mode 77.76 MHz Analog Any digital feedback mode 12E1 mode 77.76 MHz Analog 12E1 mode 16DS1 mode 12E1 mode 16E1 mode Select T4 DPLL Select T0 DPLL 12E1 Select T4 DPLL Select T0 DPLL 16DS1 Select T4 DPLL Select T0 DPLL 12E1 Select T4 DPLL Select T0 DPLL 16E1 60 1400 60 1400 500 250 200 150 3800 3800 500 250 400 220 900 3800 pk-pk (ns) 0.6 5 0.6 5 2.3 1.5 1.2 1.0 13 18 2.3 1.5 2.0 1.2 4.5 13 Revision 5/November 2006 (c) Semtech Corp. Page 30 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 12 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) T0 DPLL Mode T4 DPLL Mode T4 APLL Input Mux Jitter Level (typ) rms (ps) 2.048 2.059 2.059 2.059 2.316 2.316 2.731 2.731 2.731 2.796 3.088 3.088 3.088 3.088 3.088 3.728 4.096 4.096 4.296 4.86 5.728 6.144 6.144 6.144 6.176 6.176 6.176 via Digital1, or Digital2 (not O1) via Digital1, or Digital2 (not O1) (not O4) (not O4) (not O1) via Digital1, or Digital2 (not O1) via Digital1, or Digital2 (not O1) (not O1) (not O4) (not O1) (not O4) (not O4) via Digital1, or Digital2 (not O1) Any digital feedback mode 16DS1 mode 16E1 mode 24DS1 mode 77.76 MHz Analog Any digital feedback mode 77.76 MHz Analog Any digital feedback mode 12E1 mode 16DS1 mode E3 mode 77.76 MHz mode E3 mode 12E1 mode 16DS1 mode DS3 mode DS3 mode 24DS1 mode 16DS1 mode 24DS1 mode 16E1 mode Select T4 DPLL Select T0 DPLL 16DS1 Select T4 DPLL Select T0 DPLL 24DS1 Select T4 DPLL Select T0 DPLL 16E1 Select T4 DPLL Select T4 DPLL Select T0 DPLL 24DS1 Select T4 DPLL Select T4 DPLL Select T4 DPLL Select T4 DPLL Select T4 DPLL Select T0 DPLL 12E1 Select T4 DPLL Select T0 DPLL 16DS1 3800 200 150 760 110 110 400 220 250 110 110 110 110 3800 3800 110 3800 3800 120 60 120 900 500 250 760 200 150 pk-pk (ns) 18 1.2 1.0 2.6 0.75 0.75 1.5 1.2 1.6 1.0 0.75 0.75 0.75 13 18 1.0 13 18 1.0 0.6 1.0 4.5 2.3 1.5 2.6 1.2 1.0 FINAL DATASHEET Revision 5/November 2006 (c) Semtech Corp. Page 31 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 12 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) T0 DPLL Mode T4 DPLL Mode T4 APLL Input Mux Jitter Level (typ) rms (ps) 6.176 6.176 6.48 6.48 6.48 8.192 8.192 8.192 8.192 8.192 8.192 8.235 9.264 9.264 9.264 10.923 11.184 12.288 12.288 12.288 12.352 12.352 12.352 12.352 12.352 via Digital1, or Digital2 (not O1) 12.352 via Digital1, or Digital2 (not O1) 16.384 16.384 via Digital1, or Digital2 (not O1) via Digital1, or Digital2 (not O1) (not O1) (not O1) via Digital1, or Digital2 (not O1) via Digital1, or Digital2 (not O1) 77.76 MHz Analog Any digital feedback mode 77.76 MHz analog 77.76 MHz digital 12E1 mode 16E1 mode 77.76 MHz Analog Any digital feedback mode 16DS1 mode 24DS1 mode 16E1 mode 12E1 mode 24DS1 mode 16DS1 mode 77.76 MHz Analog Any digital feedback mode 12E1 mode 16E1 mode DS3 mode 12E1 mode 16DS1 mode 77.76 MHz mode 16E1 mode 24DS1 mode Select T4 DPLL Select T4 DPLL Select T0 DPLL 16E1 Select T4 DPLL Select T0 DPLL 24DS1 Select T4 DPLL Select T4 DPLL Select T0 DPLL 12E1 Select T4 DPLL Select T0 DPLL 16DS1 3800 3800 60 60 60 900 250 400 220 3800 3800 760 110 110 110 250 110 900 500 250 110 760 200 150 3800 3800 900 250 pk-pk (ns) 13 18 0.6 0.6 0.6 4.5 1.6 2.0 1.2 13 18 2.6 0.75 0.75 0.75 1.6 1.0 4.5 2.3 1.5 0.75 2.6 1.2 1.0 13 18 4.5 1.6 FINAL DATASHEET Revision 5/November 2006 (c) Semtech Corp. Page 32 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 12 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) T0 DPLL Mode T4 DPLL Mode T4 APLL Input Mux Jitter Level (typ) rms (ps) 16.384 16.384 16.384 via Digital1, or Digital2 (not O1) 16.384 via Digital1, or Digital2 (not O1) 16.469 17.184 18.528 18.528 18.528 19.44 19.44 19.44 21.845 22.368 24.576 24.576 24.576 24.704 24.704 24.704 24.704 25.92 25.92 32.768 32.768 32.768 34.368 37.056 37.056 77.76 MHz Analog Any digital feedback mode 16DS1 mode 24DS1 mode 77.76 MHz analog 77.76 MHz digital 16E1 mode 12E1 mode 24DS1 mode 16DS1 mode 77.76 MHz analog 77.76 MHz digital 16E1 mode 24DS1 mode E3 mode 24DS1 mode DS3 mode 12E1 mode 16DS1 mode 16E1 mode E3 mode 24DS1 mode 77.76MHz mode 16E1 mode Select T4 DPLL Select T0 DPLL 16E1 Select T4 DPLL Select T4 DPLL Select T0 DPLL 24DS1 Select T4 DPLL Select T4 DPLL Select T4 DPLL Select T0 DPLL 12E1 Select T4 DPLL Select T0 DPLL 16DS1 Select T4 DPLL Select T0 DPLL 16E1 Select T4 DPLL Select T4 DPLL 400 220 3800 3800 760 120 110 110 110 60 60 60 250 110 900 500 250 110 760 200 150 60 60 250 400 220 120 110 110 pk-pk (ns) 2.0 1.2 13 18 2.6 1.0 0.75 0.75 0.75 0.6 0.6 0.6 1.6 1.0 4.5 2.3 1.5 0.75 2.6 1.2 1.0 0.6 0.6 1.6 2.0 1.2 1.0 0.75 0.75 FINAL DATASHEET Revision 5/November 2006 (c) Semtech Corp. Page 33 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 12 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) T0 DPLL Mode T4 DPLL Mode T4 APLL Input Mux Jitter Level (typ) rms (ps) 37.056 38.88 38.88 38.88 44.736 49.152 (O4 only) 49.152 (O4 only) 49.152 (O1 only) 49.408 (O4 only) 49.408 (O4 only) 49.408 (O1 only) 51.84 51.84 65.536 (O4 only) 65.536 (O4 only) 65.536 (O1 only) 68.736 74.112 (O4 only) 74.112 (O4 only) 74.112 (O1 only) 77.76 77.76 77.76 89.472 (O4 only) 98.304 (O1 only) 98.816 (O1 only) 131.07 (O1 only) 137.47 (O4 only) 148.22 (O1 only) 77.76 MHz analog 77.76 MHz digital 12E1 mode 16DS1 mode 77.76 MHz analog 77.76 MHz digital 16E1 mode 24DS1 mode 77.76 MHz analog 77.76 MHz digital 12E1 mode 16DS1 mode 16E1 mode 24DS1 mode E3 mode E3 mode 24DS1 mode 77.76 MHz mode DS3 mode 77.76 MHz mode DS3 mode 12E1 mode 16DS1 mode 16E1 mode Select T0 DPLL 24DS1 Select T4 DPLL Select T4 DPLL Select T4 DPLL Select T0 DPLL 12E1 Select T4 DPLL Select T0 DPLL 16DS1 Select T4 DPLL Select T0 DPLL 16E1 Select T4 DPLL Select T4 DPLL Select T0 DPLL 24DS1 Select T4 DPLL Select T4 DPLL Select T4 DPLL 110 60 60 60 110 500 250 900 200 150 760 60 60 400 220 250 120 110 110 110 60 60 60 110 900 760 250 120 110 pk-pk (ns) 0.75 0.6 0.6 0.6 1.0 2.3 1.5 4.5 1.2 1.0 2.6 0.6 0.6 2.0 1.2 1.6 1.0 0.75 0.75 0.75 0.6 0.6 0.6 1.0 4.5 2.6 1.6 1.0 0.75 FINAL DATASHEET Revision 5/November 2006 (c) Semtech Corp. Page 34 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 12 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) T0 DPLL Mode T4 DPLL Mode T4 APLL Input Mux Jitter Level (typ) rms (ps) 155.52 (O4 only) 155.52 (O1 only) 155.52 (O1 only) 311.04 (O1 only) 311.04 (O1 only) 77.76 MHz analog 77.76 MHz digital 77.76 MHz analog 77.76 MHz digital 77.76 MHz mode Select T4 DPLL 60 60 60 60 60 pk-pk (ns) 0.6 0.6 0.6 0.6 0.6 FINAL DATASHEET Table 13 Frequency Divider Look-up APLL Frequency 311.04 274.944 178.944 148.224 131.072 98.816 98.304 APLL/2 155.52 137.472 89.472 74.112 65.536 49.408 49.152 APLL/4 77.76 68.376 44.736 37.056 32.768 24.704 24.576 APLL/6 51.84 24,704 21.84533 16.46933 16.384 APLL/8 38.88 34.368 22.368 18.528 16.384 12.352 12.288 APLL/12 25.92 12.352 10.92267 8.234667 8.192 APLL/16 19.44 17.184 11.184 9.264 8.192 6.176 6.144 APLL/48 6.48 5.728 3.728 3.088 2.730667 2.058667 2.048 APLL/64 4.86 4.296 2.796 2.316 2.048 1.544 1.536 Note...All frequencies in MHz Revision 5/November 2006 (c) Semtech Corp. Page 35 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 14 T0 APLL Frequencies T0 APLL Frequency 311.04 MHz 311.04 MHz 98.304 MHz 131.072 MHz 148.224 MHz 98.816 MHz T0 Mode Normal (digital feedback) Normal (analog feedback) 12E1 (digital feedback) 16E1 (digital feedback) 24DS1 (digital feedback) 16DS1 (digital feedback) Do not use Do not use T0 DPLL Frequency Control Register Bits Reg. 65 Bits[2:0] 000 001 010 011 100 101 110 111 Output Jitter Level ns (pk-pk) <0.5 <0.5 <2 <2 <2 <2 - FINAL DATASHEET Table 15 T4 APLL Frequencies T4 APLL Frequency 311.04 MHz 311.04 MHz 98.304 MHz 131.072 MHz 148.224 MHz 98.816 MHz 274.944 MHz 178.944 MHz 98.304 MHz 131.072 MHz 148.224 MHz 98.816 MHz T4 Mode T4 Forward DFS T4 DPLL Freq. Control Frequency Register Bits (MHz) Reg. 64 Bits [2:0] 77.76 77.76 24.576 32.768 37.056 (2*18.528) 24.704 68.736 (2*34.368) 44.736 000 001 010 011 100 101 110 111 XXX XXX XXX XXX T4 APLL for T0 Enable Register Bit Reg. 65Bit 6 0 0 0 0 0 0 0 0 1 1 1 1 T0 Freq. to T4 APLL Register Bits Reg. 65 Bits [5:4] XX XX XX XX XX XX XX XX 00 01 10 11 Output Jitter Level ns (pk-pk) <0.5 <0.5 <0.5 <0.5 <0.5 <0.5 <0.5 <0.5 <2 <2 <2 <2 Squelched Normal 12E1 16E1 24DS1 16DS1 E3 DS3 T0-12E1 T0-16E1 T0-24DS1 T0-16DS1 Revision 5/November 2006 (c) Semtech Corp. Page 36 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 16 O1 to O4 Output Frequency Selection Output Frequency for given "Value in Register" for each Output Port's cnfg_output_frequency Register Value in Register 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 O1, Reg. 62 Bits [7:4] Off 2 kHz 8 kHz T0 APLL/2 Digital1 T0 APLL/1 T0 APLL/16 T0 APLL/12 T0 APLL/8 T0 APLL/6 T0 APLL/4 T4 APLL/64 T4 APLL/48 T4 APLL/16 T4 APLL/8 T4 APLL/4 O2, Reg. 60 Bits [7:4] Off 2 kHz 8 kHz Digital2 Digital1 T0 APLL/48 T0 APLL/16 T0 APLL/12 T0 APLL/8 T0 APLL/6 T0 APLL/4 T4 APLL/64 T4 APLL/48 T4 APLL/16 T4 APLL/8 T4 APLL/4 O3, Reg. 61 Bits [3:0] Off 2 kHz 8 kHz Digital2 Digital1 T0 APLL/48 T0 APLL/16 T0 APLL/12 T0 APLL/8 T0 APLL/6 T0 APLL/4 T4 APLL/64 T4 APLL/48 T4 APLL/16 T4 APLL/8 T4 APLL/4 O4, Reg. 62 Bits [3:0] Off 2 kHz 8 kHz Digital2 Digital1 T0 APLL/48 T0 APLL/16 T0 APLL/12 T0 APLL/8 T0 APLL/6 T0 APLL/4 T4 APLL/2 T4 APLL/48 T4 APLL/16 T4 APLL/8 T4 APLL/4 FINAL DATASHEET "Digital" Frequencies FrSync, MFrSync, 2 kHz and 8 kHz Clock Outputs It can be seen from Table 16 (O1 to O4 output frequency selection) that frequencies listed as Digital1 and Digital2 can be selected. Digital1 is a single frequency selected from the range shown in Table 17. Digital2 is another single frequency selected from the same range. The T0 LF output DFS block shown in the diagram and clocked either by the T0 77M output DFS block or via the T0 output APLL, generates these two frequencies. The input clock frequency of the DFS is always 77.76 MHz and as such has a period of approximately 12 ns. The jitter generated on the Digital outputs is relatively high, due to the fact that they do not pass through an APLL for jitter filtering. The minimum level of jitter is when the T0 path is in analog feedback mode, when the pk-pk jitter will be approximately 12 ns (equivalent to a period of the DFS clock). The maximum jitter is generated when in digital feedback mode, when the total is approximately 17 ns. Revision 5/November 2006 (c) Semtech Corp. It can be seen from Table 16 (O1 to O4 Output Frequency Selection) that frequencies listed as 2 kHz and 8 kHz can be selected. Whilst the FrSync and MFrSync outputs are always supplied from the T0 path, the 2 kHz and 8 kHz options available from the O1 to O4 outputs are all supplied from either the T0 or T4 path (Reg. 7A bit 7). The outputs can be either clocks (50:50 mark-space) or pulses and can be inverted. When pulses are configured on the output, the pulse width will be one cycle of the output of O3 (O3 must be configured to generate at least 1544 kHz to ensure that pulses are generated correctly). Figure 11 shows the various options with the 8 kHz controls in Reg. 7A. There is an identical arrangement with Reg. 7A bits [1:0] and the 2 kHz/MFrSync outputs. Outputs FrSync and MFrSync can be disabled via Reg. 63 bits [7:6]. www.semtech.com Page 37 ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 11 Control of 8k Options. 03 output FrSync/8kHz output a) Clock non-inverted, Reg.7A[3:2] = 00 03 output FrSync/8kHz output c) Clock inverted, Reg.7A[3:2] = 10 FINAL DATASHEET 03 output FrSync/8kHz output b) Pulse non-inverted, Reg.7A[3:2] = 01 03 output FrSync/8kHz output d) Pulse inverted, Reg.7A[3:2] = 11 F8522_016outputoptions8k_01 Table 17 Digital Frequency Selections Digital1 Control Reg.39 Bits [5:4] 00 01 10 11 00 01 10 11 Digital1 SONET/ SDH Reg. 38 Bit5 0 0 0 0 1 1 1 1 Digital1 Freq. (MHz) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 Digital2 Control Reg. 39 Bits[7:6] 00 01 10 11 00 01 10 11 Digital2 SONET/SDH Reg.38 Bit6 0 0 0 0 1 1 1 1 Digital2 Freq. (MHz) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 Power-On Reset The Power-On Reset (PORB) pin resets the device if forced Low. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Reset must be asserted at power on, and may be re-asserted at any time to restore defaults. This is implemented simply using an external capacitor to GND along with the internal pull-up resistor. The ACS8522 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High. ACS8522 address and data are transmitted and received LSB first. Address, read/write control and data on the SDI pin are latched into the device on the rising edge of the SCLK. During a read operation, serial data output on the SDO pin can be read out of the device on either the rising or falling edge of the SCLK depending on the logic level of CLKE. For standard Motorola SPI compliance, data should be clocked out of the SDO pin on the rising edge of the SCLK so that it may be latched into the microprocessor on the falling edge of the SCLK. Figure 12 and Figure 13 show the timing diagrams of write and read accesses for this interface. During read access, the output data SDO is clocked out on the rising edge of SCLK when the active edge selection control bit CLKE is 0 and on the falling edge when CLKE is 1. The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1). Serial Interface The ACS8522 device has a serial interface which can be SPI compatible. The Motorola SPI convention is such that address and data is transmitted and received MSB first. On the Revision 5/November 2006 (c) Semtech Corp. Page 38 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 12 Read Access Timing for SERIAL Interface CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 SCLK tsu1 _ FINAL DATASHEET Figure 12 and Figure 13 show the timing diagrams of read and write accesses for this mode. tpw2 th2 th1 R/W tpw1 SDI A0 A1 A2 A3 A4 A5 A6 td1 td2 SDO Output not driven, pulled low by internal resistor D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 SCLK _ SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 td2 SDO Output not driven, pulled low by internal resistor D0 D1 D2 D3 D4 D5 D6 D7 F8526D_013ReadAccSerial_01 Table 18 Read Access Timing for SERIAL Interface (For use with Figure 12) Symbol tsu1 tsu2 td1 td2 tpw1 tpw2 th1 th2 tp Parameter Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid Delay CSBrising edge to SDO high-Z SCLK Low time SCLK High time Hold SDI valid after SCLKrising edge Hold CSB Low after SCLKrising edge, for CLKE = 0 Hold CSB Low after SCLKfalling edge, for CLKE = 1 Time between consecutive accesses (CSBrising edge to CSBfalling edge) MIN 4 ns 14 ns 22 ns 22 ns 6 ns 5 ns 10 ns TYP MAX 18 ns 16 ns - Revision 5/November 2006 (c) Semtech Corp. Page 39 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Figure 13 Write Access Timing for SERIAL Interface FINAL DATASHEET CSB tsu2 SCLK tsu1 _ tpw2 th2 th1 R/W tpw1 SDI A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 SDO Output not driven, pulled low by internal resistor F8525D_014WriteAccSerial_01 Table 19 Write Access Timing for SERIAL Interface (For use with Figure 13) Symbol tsu1 tsu2 tpw1 tpw2 th1 th2 tp Parameter Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge SCLK Low time SCLK High time Hold SDI valid after SCLKrising edge Hold CSB Low after SCLKrising edge Time between consecutive accesses (CSBrising edge to CSBfalling edge) MIN 4 ns 14 ns 22 ns 22 ns 6 ns 5 ns 10 ns TYP MAX - Revision 5/November 2006 (c) Semtech Corp. Page 40 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Register Map Each Register, or register group, is described in the following Register Map (Table 20) and subsequent Register Description Tables. FINAL DATASHEET cleared by writing a 1 into each bit of the field (writing a 0 value into a bit will not affect the value of the bit). Configuration Registers Register Organization The ACS8522 SETS LITE uses a total of 95 eight-bit register locations, identified by a Register Name and corresponding hexadecimal Register Address. They are presented here in ascending order of Reg. address. and each Register is organized with the most-significant bit positioned in the left-most bit, and bit significance decreasing towards the right-most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. Several data fields are spread across multiple registers, as shown in the Register Map, Table 20.Shaded areas in the map are "don't care" and writing either 0 or 1 to them will not affect any function of the device.Bits labelled "Set to 0" or "Set to 1" must be set as stated during initialization of the device, either following power- up, or after a power-on reset (POR). Failure to correctly set these bits may result in the device operating in an unexpected way. CAUTION! Do not write to any undefined register addresses as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. Multi-word Registers For multi-word registers (e.g. Reg. 70 and 71), all the words have to be written to their separate addresses, and without any other access taking place, before their combined value can take effect. If the sequence is interrupted the sequence of writes will be ignored. Reading a multi-word address freezes the other address words of a multi-word address so that the bytes all correspond to the same complete word. Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some can be pin-set. All configuration registers can be read out over the serial port. Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Interrupt Enable and Clear Interrupt requests are flagged on pin INTREQ; the active state (High or Low) is programmable and the pin can either be driven, or set to high impedance when nonactive (Reg 7D refers). Bits in the interrupt status register are set (High) by the following conditions; 1. Any reference source becoming valid or going invalid. 2. A change in the operating state (e.g. Locked, Holdover 3. A brief loss of the currently selected reference source. All interrupt sources, see Reg. 05, Reg. 06 and Reg. 08, are maskable via the mask register, each one being enabled by writing a 1 to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted.All interrupts are cleared by writing a 1 to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive. Defaults Each Register is given a defined default value at reset and these are listed in the Map and Description Tables. However, some read-only status registers may not necessarily show the same default values after reset as those given in the tables. This is because they reflect the status of the device which may have changed in the time it takes to carry out the read, or through reasons of configuration. In the same way, the default values given for shaded areas could also take different values to those stated. www.semtech.com Register Access Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_id and chip_revision registers. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be Revision 5/November 2006 (c) Semtech Corp. Page 41 ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 20 Register Map RO = Read Only R/W = Read/Write chip_id (RO) chip_revision (RO) test_register1 (R/W, Bit 7 RO) sts_interrupts (R/W) Address (hex) Default (hex) Register Name Data Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) FINAL DATASHEET 00 01 02 03 05 06 4A 21 00 14 FF 3F 00 50 41 00 00 00 00 00 00 Out-of-band alarm (soft) 66 66 66 32 40 05 00 00 03 03 00 0F CA 40 0D 08 C2 FD 99 00 00 88 76 00 00 00 SEC3 interrupt not masked operating_ mode interrupt not masked main_ref_ failed interrupt not masked auto_ averaging auto_BW_sel Set to zero lock_T4_to T0 phalarm_ timeout T4_dig_ feedback dig2_sonsdh digital2_frequency divn_SEC1 divn_SEC2 divn_SEC3 divn_SEC4 lock8k_SEC1 lock8k_SEC2 lock8k_SEC3 lock8k_SEC4 Out-of-band alarm (hard) SEC3 T4_status phase_alarm SEC3 valid change operating_ mode main_ref_ failed disable_180 Device part number [7:0] 8 least significant bits of the chip ID Device part number [15:8] 8 most significant bits of the chip ID Chip revision number [7:0] resync_ analog Set to zero SEC2 valid change 8K edge polarity SEC1 valid change SEC4 valid change Bits [18:16] of current DPLL frequency Set to zero Set to zero sts_current_DPLL_frequency, see OC/OD sts_interrupts (R/W) sts_operating (RO) sts_priority_table (RO) 07 08 09 0A 0B T4_DPLL_Lock T0_DPLL_freq _soft_alarm Highest priority validated source 3rd highest priority validated source T4_DPLL_freq _soft_alarm T0_DPLL_operating_mode Currently selected source 2nd highest priority validated source sts_current_DPLL_frequency [7:0] 0C (RO) sts_sources_valid (RO) sts_reference_sources (RO) Status of inputs: Inputs SEC1 & SEC2 11 SEC3 13 SEC4 14 cnfg_ref_selection_priority (R/W) (SEC2 & SEC1) 19 (SEC3) 1B (SEC4) 1C cnfg_ref_source_frequency (R/W) (SEC1) 22 (SEC2) 23 (SEC3) 27 (SEC4) 28 cnfg_operating_mode (R/W) force_select_reference_source (R/W) cnfg_input_mode (R/W) cnfg_T4_path (R/W) cnfg_dig_outputs_sonsdh (R/W) cnfg_digtial_frequencies (R/W) cnfg_differential_outputs (R/W) cnfg_auto_bw_sel cnfg_nominal_frequency (R/W) cnfg_holdover_frequency (R/W) cnfg_holdover_modes (R/W) 32 33 34 35 38 39 3A 3B [7:0] 3C [7:0] 3E [15:8] 3F 40 [18:16] 07 0E 0F Bits [7:0] of current DPLL frequency Bits [15:8] of current DPLL frequency Bits [18:16] of current DPLL frequency SEC2 No activity alarm Phase lock alarm Out-of-band alarm (soft) SEC1 SEC4 Out-of band alarm (hard) No activity alarm Phase lock alarm [15:8] 0D 00 Status of SEC2 Input Status of SEC3 Input Status of SEC1 Input Status of SEC4 Input programmed_priority programmed_priority bucket_id_SEC1 bucket_id_SEC2 bucket_id_SEC3 bucket_id_SEC4 reference_source_frequency_SEC1 reference_source_frequency_SEC2 reference_source_frequency_SEC3 reference_source_frequency_SEC4 TO_DPLL_operating_mode forced_reference_source XO_ edge man_holdover extsync_en ip_sonsdhb T4_forced_reference_source reversion_ mode dig1_sonsdh digital1_frequency O1_LVDS_PECL T0_lim_int Nominal frequency [7:0] Nominal frequency [15:8] Holdover frequency [7:0] Holdover frequency [15:8] [15:8] 3D 99 fast_averaging read_average mini_holdover_mode DPLL frequency offset limit [7:0] Holdover frequency [18:16] (with Registers 3E and 3F above) DPLL frequency offset limit [9:8] cnfg_DPLL_freq_limit (R/W) [7:0] 41 [9:8] 42 cnfg_interrupt_mask (R/W) [7:0] 43 [15:8] 44 SEC2 interrupt not masked SEC1 interrupt not masked SEC4 interrupt not masked Revision 5/November 2006 (c) Semtech Corp. Page 42 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 20 Register Map (cont...) RO = Read Only R/W = Read/Write Address (hex) Default (hex) Register Name Data Bit 7 (MSB) 6 T4_status interrupt not masked divn_value [7:0] divn_value [13:8] freq_mon_clk los_flag_ on_ TDO ultra_fast_ switch ext_switch PBO_freeze PBO_en freq_monitor_ soft_enable freq_monitor_ hard_enable 5 4 3 2 1 0 (LSB) FINAL DATASHEET cnfg_interrupt_mask cont.[23:16] 45 00 cnfg_freq_divn (R/W) cnfg_monitors (R/W) [7:0] 46 [13:8] 47 48 49 4A 4B 4C FF 3F 05 23 23 00 00 Freq limit Phase loss enable cnfg_freq_mon_threshold (R/W) cnfg_current_freq_mon_ threshold (R/W) cnfg_registers_source_select (R/W) sts_freq_measurement (RO) cnfg_DPLL_soft_limit (R/W) soft_frequency_alarm_threshold [3:0] current_soft_frequency_alarm_threshold [3:0] T4_T0_select hard_frequency_alarm_threshold [3:0] current_hard_frequency_alarm_threshold [3:0] frequency_measurement_channel_select [3:0] freq_measurement_value [7:0] DPLL Frequency Soft Alarm Limit [6:0] Resolution = 0.628 ppm 4D 8E cnfg_upper_threshold_0 (R/W) cnfg_lower_threshold_0 (R/W) cnfg_bucket_size_0 (R/W) cnfg_decay_rate_0 (R/W) cnfg_upper_threshold_1 (R/W) cnfg_lower_threshold_1 (R/W) cnfg_bucket_size_1 (R/W) cnfg_decay_rate_1 (R/W) cnfg_upper_threshold_2 (R/W) cnfg_lower_threshold_2 (R/W) cnfg_bucket_size_2 (R/W) cnfg_decay_rate_2 (R/W) cnfg_upper_threshold_3 (R/W) cnfg_lower_threshold_3 (R/W) cnfg_bucket_size_3 (R/W) cnfg_decay_rate_3 (R/W) 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5F 06 04 08 01 06 04 08 01 06 04 08 01 06 08 01 80 06 84 C0 05 01 T4 for measuring T0 phase T4 APLL for T0 E1/DS1 MFrSync_en Leaky Bucket Configuration 0: Activity alarm set threshold [7:0] Leaky Bucket Configuration 0: Activity alarm reset threshold [7:0] Leaky Bucket Configuration 0: Activity alarm bucket size [7:0] Leaky Bucket Cfg 0: decay_rate [1:0] Leaky Bucket Configuration 1: Activity alarm set threshold [7:0] Leaky Bucket Configuration 1: Activity alarm reset threshold [7:0] Leaky Bucket Configuration 1: Activity alarm bucket size [7:0] Leaky Bucket Cfg 1: decay_rate [1:0] Leaky Bucket Configuration 2: Activity alarm set threshold [7:0] Leaky Bucket Configuration 2: Activity alarm reset threshold [7:0] Leaky Bucket Configuration 2: Activity alarm bucket size [7:0] Leaky Bucket Cfg 2: decay_rate [1:0] Leaky Bucket Configuration 3: Activity alarm set threshold [7:0] Leaky Bucket Configuration 3: Activity alarm reset threshold [7:0] Leaky Bucket Configuration 3: Activity alarm bucket size [7:0] Leaky Bucket Cfg 3: decay_rate [1:0] output_freq_O2 output_freq_O3 output_freq_O1 FrSync_en T4_DPLL_frequency T0 Freq to T4 APLL T0_DPLL_frequency output_freq_O4 5D 04 cnfg_output_frequency (R/W)(O2) 60 (O3) 61 (O4 & O1) 62 (MFrSync) 63 cnfg_T4_DPLL_frequency (R/W) cnfg_T0_DPLL_frequency (R/W) 64 65 cnfg_T4_DPLL_bw (R/W) cnfg_T0_DPLL_locked_bw (R/W) cnfg_T0_DPLL_acq_bw (R/W) cnfg_T4_DPLL_damping (R/W) cnfg_T0_DPLL_damping (R/W) cnfg_T4_DPLL_PD2_gain (R/W) cnfg_T0_DPLL_PD2_gain (R/W) cnfg_phase_offset (R/W) 66 67 69 6A 6B 6C 00 0D 0F 13 13 C2 T4_PD2_gain_ enable T0_PD2_gain_ enable T4_PD2_gain_alog_8K [6:4] T0_PD2_gain_alog_8K [6:4] T4_PD2_gain_alog [6:4] T0_PD2_gain_alog [6:4] phase_offset_value[7:0] phase_offset_value[15:8] PBO_phase_offset [5:0] Fine limit Phase loss enable (1) No activity for phase loss Test bit Set to 1 T4_DPLL_bandwidth [1:0] T0_DPLL_locked_bandwidth [4:0] T0_acquisition_bandwidth [4:0] T4_damping [2:0] T0_damping [2:0] T4_PD2_gain_digital [2:0] T0_PD2_gain_digital [2:0] 6D C2 00 00 00 A2 [7:0] 70 [15:8] 71 72 cnfg_PBO_phase_offset (R/W) cnfg_phase_loss_fine_limit (R/W) 73 phase_loss_fine_limit [2:0] Revision 5/November 2006 (c) Semtech Corp. Page 43 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 20 Register Map (cont...) RO = Read Only R/W = Read/Write cnfg_phase_loss_coarse_limit (R/W) cnfg_phasemon (R/W) sts_current_phase (RO) Address (hex) Default (hex) Register Name Data Bit 7 (MSB) Coarse limit Phase loss enable (2) Input noise window enable current_phase[7:0] current_phase[15:8] Timeout value in 2s intervals [5:0] 2k_8k_from_ T4 indep_FrSync/ MFrSync ph_offset_ ramp GPO interrupt enable protection_value Interrupt tristate enable Interrupt polarity enable Sync_OC-N_ rates 8k_invert 8k_pulse 2k_invert 2k_pulse Sync_phase 6 Wide range enable 5 Enable Multi Phase resp. 4 3 2 1 0 (LSB) FINAL DATASHEET 74 85 Phase loss coarse limit in UI pk-pk [3:0] 76 [7:0] 77 [15:8] 78 79 7A 7B 7C 06 00 00 32 00 00 2B cnfg_phase_alarm_timeout (RO) cnfg_sync_pulses (R/W) cnfg_sync_phase (R/W) cnfg_sync_monitor (R/W) cnfg_interrupt (R/W) 7D 02 cnfg_protection(R/W) 7E 85 Revision 5/November 2006 (c) Semtech Corp. Page 44 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Register Descriptions Address (hex): 00 Register Name chip_id Description (RO) 8 least significant bits of the Default Value chip ID. Bit 3 chip_id[7:0] Bit No. [7:0] Description chip_id Least significant byte of the 2-byte device ID Bit Value 4A (hex) Value Description Bit 2 Bit 1 0100 1010 FINAL DATASHEET Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Address (hex): 01 Register Name chip_id Description (RO) 8 most significant bits of the Default Value chip ID. Bit 3 Bit 2 Bit 1 0010 0001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 chip_id[15:8] Bit No. [7:0] Description chip_id Most significant byte of the 2-byte device ID Bit Value 21 (hex) Value Description Address (hex): 02 Register Name Bit 7 chip_revision Bit 6 Bit 5 Description Bit 4 (RO) Silicon revision of the device. Default Value Bit 3 Bit 2 Bit 1 0000 0000 Bit 0 chip_revision[7:0] Bit No. [7:0] Description chip_revision Silicon revision of the device Bit Value 00 (hex) Value Description Revision 5/November 2006 (c) Semtech Corp. Page 45 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 03 Register Name test_register1 Description FINAL (R/W) Register containing various Default Value test controls (not normally used). Bit 3 Set to zero Bit Value 0 1 0 1 Bit 2 Bit 1 DATASHEET 0001 0000 Bit 7 phase_alarm Bit No. 7 6 Bit 6 disable_180 Description Bit 5 Bit 4 resync_analog Bit 0 Set to zero 8k Edge Polarity Set to zero Value Description T0 DPLL reporting phase locked. T0 DPLL reporting phase lost. phase_alarm (phase alarm (R/O)) Instantaneous result from T0 DPLL disable_180 Normally the DPLL will try to lock to the nearest edge (180) for the first 2 seconds when locking to a new reference. If the DPLL does not determine that it is phase locked after this time, then the capture range reverts to 360, which corresponds to frequency and phase locking. Forcing the DPLL into frequency locking mode may reduce the time to frequency lock to a new reference by up to 2 seconds. However, this may cause an unnecessary phase shift of up to 360 when the new and old references are very close in frequency and phase. Not used. resync_analog (analog dividers re-synchronization) The analog output dividers include a synchronization mechanism to ensure phase lock at low frequencies between the input and the output. T0 DPLL automatically determines frequency lock enable. T0 DPLL forced to always frequency and phase lock. 5 4 0 1 Analog divider only synchronized during first 2 seconds after power-up. Analog dividers always synchronized.This keeps the clocks divided down from the APLL output, in sync with equivalent frequency digital clocks in the DPLL. Hence ensuring that 6.48 MHz output clocks, and above, are in sync with the DPLL even though only a 77.76 MHz clock drives the APLL. Lock to falling clock edge. Lock to rising clock edge. 3 2 Test Control Leave unchanged or set to 0 8k Edge Polarity When lock 8k mode is selected for the current input reference source, this bit allows the system to lock on either the rising or the falling edge of the input clock. Test Control Leave unchanged or set to zero Test Control Leave unchanged or set to zero 0 0 1 1 0 0 0 - Revision 5/November 2006 (c) Semtech Corp. Page 46 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 05 Register Name sts_interrupts Description FINAL (R/W) Bits [7:0] of the interrupt status register. Bit 3 SEC2 valid change Bit 2 SEC1 valid change Value Description Default Value DATASHEET 1111 1111 Bit 7 SEC3 valid change Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Description SEC3 valid change Interrupt indicating that input SEC3 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. Not used. SEC2 valid change Interrupt indicating that input SEC2 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. SEC1 valid change Interrupt indicating that input SEC1 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. Not used. Bit Value 0 1 Input SEC3 has not changed status (valid/invalid). Input SEC3 has changed status (valid/invalid). Writing 1 resets the input to 0. Input SEC2 has not changed status (valid/invalid). Input SEC2 has changed status (valid/invalid). Writing 1 resets the input to 0. Input SEC1 has not changed status (valid/invalid). Input SEC1 has changed status (valid/invalid). Writing 1 resets the input to 0. - [6:4] 3 0 1 2 0 1 [1:0] - Address (hex): 06 Register Name sts_interrupts Description (R/W) bits [15:8] of the interrupt status register. Bit 3 Bit 2 Default Value 0111 1111 Bit 7 operating_ mode Bit No. 7 Bit 6 main_ref_failed Bit 5 Bit 4 Bit 1 Bit 0 SEC4 valid change Description operating_mode Interrupt indicating that the operating mode has changed. Latched until reset by software writing a 1 to this bit. main_ref_failed Interrupt indicating that input to the T0 DPLL has failed. This interrupt will be raised after 2 missing input cycles. This is much quicker than waiting for the input to become invalid. This input is not generated in Free-run or Holdover modes. Latched until reset by software writing a 1 to this bit. Bit Value 0 1 Value Description Operating mode has not changed. Operating mode has changed. Writing 1 resets the input to 0. Input to the T0 DPLL is valid. Input to the T0 DPLL has failed. Writing 1 resets the input to 0. 6 0 1 Revision 5/November 2006 (c) Semtech Corp. Page 47 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 06 (cont...) Register Name sts_interrupts Description FINAL (R/W) bits [15:8] of the interrupt status register. Bit 3 Bit 2 Default Value DATASHEET 0111 1111 Bit 7 operating_ mode Bit No. [5:1] 0 Bit 6 main_ref_failed Bit 5 Bit 4 Bit 1 Bit 0 SEC4 valid change Description Not used. SEC4 valid change Interrupt indicating that input SEC4 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. Bit Value 0 1 Value Description Input SEC4 has not changed status (valid/invalid). Input SEC4 has changed status (valid/invalid). Writing 1 resets the input to 0. Address (hex): 07 Register Name sts_current_DPLL_frequency [18:16] Bit 6 Bit 5 Description (RO) Bits [18:16] of the current DPLL frequency. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 sts_current_DPLL_frequency[18:16] Bit No. [7:3] [2:0] Description Not used. sts_current_DPLL_frequency[18:16] When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the frequency for the T0 path is reported. When this Bit 4 = 1 the frequency for the T4 path is reported. Bit Value Value Description See register description of sts_current_DPLL_frequency at address 0D hex. Address (hex): 08 Register Name sts_interrupts Description (R/W) Bits [23:16] of the interrupt Default Value status register. Bit 3 Bit 2 Bit 1 0101 0000 Bit 7 Bit 6 T4_status Bit 5 Bit 4 Bit 0 Bit No. 7 Description Not used. Bit Value - Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 48 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 08 (cont...) Register Name sts_interrupts Description FINAL (R/W) Bits [23:16] of the interrupt Default Value status register. Bit 3 Bit 2 Bit 1 DATASHEET 0101 0000 Bit 7 Bit 6 T4_status Bit 5 Bit 4 Bit 0 Bit No. 6 Description T4_status Interrupt indicating that the T4 DPLL has lost lock (if it was locked) or gained lock (if it was not locked). Latched until reset by software writing a 1 to this bit. Not used. Bit Value 0 1 Value Description Input to the T4 DPLL has not changed. Input to the T4 DPLL has lost/gained lock. Writing 1 resets the input to 0. - [5:0] - Address (hex): 09 Register Name sts_operating Description (RO) Current operating state of the device's internal state machine. Bit 3 Bit 2 Default Value 0100 0001 Bit 7 Bit 6 T4_DPLL_Lock Bit 5 T0_DPLL_freq_ soft_alarm Bit 4 T4_DPLL_freq_ soft_alarm Bit 1 T0_DPLL_operating_mode Bit 0 Bit No. 7 Description Not used. Bit Value - Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 49 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 09 (cont...) Register Name sts_operating Description FINAL (RO) Current operating state of the device's internal state machine. Bit 3 Bit 2 Default Value DATASHEET 0100 0001 Bit 7 Bit 6 T4_DPLL_Lock Bit 5 T0_DPLL_freq_ soft_alarm Bit 4 T4_DPLL_freq_ soft_alarm Bit 1 T0_DPLL_operating_mode Bit 0 Bit No. 6 Description T4_DPLL_Lock Reports current phase lock status of the T4 DPLL. The T4 DPLL does not have the same state machine as the T0 DPLL, as it does not support all the features of the TO DPLL. It can only report its state as locked or unlocked. The bit indicates that the T4 DPLL is locked by monitoring the T4 DPLL phase loss indicators, which potentially come from four sources. The four phase loss indicators are enabled by the same registers that enable them for the T0 DPLL, as follows: the fine phase loss detector enabled by Reg. 73 Bit 7, the coarse phase loss detector enabled by Reg. 74 Bit 7, the phase loss indication from no activity on the input enabled by Reg. 73 Bit 6 and phase loss from the DPLL being at its minimum or maximum frequency limits enabled by Reg. 4D Bit 7. For the T4 DPLL lock indicator (at Reg. 09 Bit 6) the bit will latch an indication of phase lost from the coarse phase lock detector such that when an indication of phase lost (or not locked) is set it stays in that phase lost or not locked state (so Reg. 09 Bit 6 =0). For this bit to give a correct current reading of the T4 DPLL locked state, then the coarse phase loss detector should be temporarily disabled (set Reg. 74 Bit 7 = 0), then the T4 locked bit can be read (Reg. 09 Bit 6), then the coarse phase loss detector should be re-enabled again (set Reg. 74 Bit 7 = 1). Once the bit is indicating "locked" (Reg. 09 Bit 6=1), it is always a correct indication and no change to the coarse phase loss detector enable is required. If at any time any cycle slips occur that trigger the coarse phase loss detector (which monitors cycle slips) then this information is latched so that the lock bit (Reg. 09 Bit 6) will go low and stay low, indicating that a problem has occurred. It is then a requirement that the coarse phase loss detector's disable/re-enable sequence is performed during a read of the T4 locked bit, in order to get a current indication of whether the T4 DPLL is locked. Bit Value 0 1 Value Description T4 DPLL not phase locked to reference source. T4 DPLL phase locked to reference source. Revision 5/November 2006 (c) Semtech Corp. Page 50 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 09 (cont...) Register Name sts_operating Description FINAL (RO) Current operating state of the device's internal state machine. Bit 3 Bit 2 Default Value DATASHEET 0100 0001 Bit 7 Bit 6 T4_DPLL_Lock Bit 5 T0_DPLL_freq_ soft_alarm Bit 4 T4_DPLL_freq_ soft_alarm Bit 1 T0_DPLL_operating_mode Bit 0 Bit No. 5 Description T0_DPLL_freq_soft_alarm The T0 DPLL has a programmable frequency limit and "soft" alarm limit. The frequency limit is the extent to which it will track a reference before limiting. The "soft" limit is the point beyond which the DPLL tracking a reference will cause an alarm. This bit reports the status of the "soft" alarm. T4_DPLL_freq_soft_alarm The T4 DPLL has a programmable frequency limit and "soft" alarm limit. The frequency limit is the extent to which it will track a reference before limiting. The "soft" limit is the point beyond which the DPLL tracking a reference will cause an alarm. This bit reports the status of the "soft" alarm. Not used. T0_DPLL_operating_mode This field is used to report the state of the internal finite state machine controlling the T0 DPLL. Bit Value 0 1 Value Description T0 DPLL tracking its reference within the limits of the programmed "soft" alarm. T0 DPLL tracking its reference beyond the limits of the programmed "soft" alarm. 4 0 1 T4 DPLL tracking its reference within the limits of the programmed "soft" alarm. T4 DPLL tracking its reference beyond the limits of the programmed "soft" alarm. 3 [2:0] 000 001 010 011 100 101 110 111 Not used. Free Run. Holdover. Not used. Locked. Pre-locked2. Pre-locked. Phase Lost. Revision 5/November 2006 (c) Semtech Corp. Page 51 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 0A Register Name sts_priority_table Description FINAL (RO) Bits [7:0] of the validated priority table. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Highest priority validated source Bit No. [7:4] Description Highest priority validated source Reports the input channel number of the highest priority validated source. When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the highest priority validated source for the T0 path is reported. When this Bit 4 = 1 the highest priority validated source for the T4 path is reported. [3:0] Currently selected source Reports the input channel number of the currently selected source. When in Non-revertive mode, this is not necessarily the same as the highest priority validated source. When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the currently selected source for the T0 path is reported. When this Bit 4 = 1 the currently selected source for the T4 path is reported. The T4 path does not have a Non-revertive mode so this will always be the same as the highest priority validated source. Bit Value 0000 0011 0100 1000 1001 Currently selected source Value Description No valid source available. Input SEC1 is the highest priority valid source. Input SEC2 is the highest priority valid source. Input SEC3 is the highest priority valid source. Input SEC4 is the highest priority valid source. 0000 0011 0100 1000 1001 All other values No source currently selected. Input SEC1 is the currently selected source. Input SEC2 is the currently selected source. Input SEC3 is the currently selected source. Input SEC4 is the currently selected source. Not used. Revision 5/November 2006 (c) Semtech Corp. Page 52 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 0B Register Name sts_priority_table Description FINAL (RO) Bits [15:8] of the validated priority table. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 3rd highest priority validated source Bit No. [7:4] Description 3rd highest priority validated source Reports the input channel number of the 3rd highest priority validated source. When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the 3rd highest priority validated source for the T0 path is reported. When this Bit 4 = 1 the value will always be zero as the T4 path does not maintain the 3rd highest priority validated source. [3:0] 2nd highest priority validated Reports the input channel number of the 2nd highest priority validated source. When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the 2nd highest priority validated source for the T0 path is reported. When this Bit 4 = 1 the 2nd highest priority validated source for the T4 path is reported. Bit Value 0000 0011 0100 1000 1001 All other values 2nd highest priority validated source Value Description No source currently selected. Input SEC1 is the currently selected source. Input SEC2 is the currently selected source. Input SEC3 is the currently selected source. Input SEC4 is the currently selected source. Not used. 0000 0011 0100 1000 1001 All other values No source currently selected. Input SEC1 is the currently selected source. Input SEC2 is the currently selected source. Input SEC3 is the currently selected source. Input SEC4 is the currently selected source. Not used. Address (hex): 0C Register Name sts_current_DPLL_frequency [7:0] Bit 6 Bit 5 Description (RO) Bits [7:0] of the current DPLL Default Value frequency. Bit 3 Bit 2 Bit 1 0000 0000 Bit 7 Bit 4 Bit 0 Bits [7:0] of sts_current_DPLL_frequency Bit No. [7:0] Description Bits [7:0] of sts_current_DPLL_frequency When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the frequency for the T0 path is reported. When this Bit 4 = 1 the frequency for the T4 path is reported. Bit Value Value Description See register description of sts_current_DPLL_frequency at address 0D hex. Revision 5/November 2006 (c) Semtech Corp. Page 53 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 0D Register Name sts_current_DPLL_frequency [15:8] Bit 6 Bit 5 Description FINAL (RO) Bits [15:8] of the current DPLL frequency. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 sts_current_DPLL_frequency[15:8] Bit No. [7:0] Description sts_current_DPLL_frequency[15:8] This value in this register is combined with the value in Reg. 0C and Reg. 07 to represent the current frequency offset of the DPLL. When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the frequency for the T0 path is reported. When this Bit 4 = 1 the frequency for the T4 path is reported. Bit Value Value Description In order to calculate the ppm offset of the DPLL with respect to the crystal oscillator frequency, the value in Reg. 07, Reg. 0D and Reg. 0C need to be concatenated. This value is a 2's complement signed integer. The value multiplied by 0.0003068 dec. will give the value in ppm offset with respect to the XO frequency, allowing for any crystal calibration that has been performed, via cnfg_nominal_frequency, Reg. 3C and 3D. The value is actually the DPLL integral path value so it can be viewed as an average frequency, where the rate of change is related to the DPLL bandwidth. If bit 3 of Reg. 3B is High then this value will freeze if the DPLL has been pulled to its min. or max. frequency. Address (hex): 0E Register Name sts_sources_valid Description (RO) 8 least significant bits of the Default Value sts_sources_valid register. Bit 3 SEC2 Description SEC3 Bit indicating if SEC3 is valid. The input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. Not used. SEC2 Bit indicating if SEC2 is valid. The input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. SEC1 Bit indicating if SEC1 is valid. The input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. Not used. Bit Value 0 1 SEC1 Value Description Input SEC3 is invalid. Input SEC3 is valid. Bit 2 Bit 1 0000 0000 Bit 7 SEC3 Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 0 [6:4] 3 0 1 Input SEC2 is invalid. Input SEC2 is valid. 2 0 1 Input SEC1 is invalid. Input SEC1 is valid. [1:0] - - Revision 5/November 2006 (c) Semtech Corp. Page 54 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 0F Register Name sts_sources_valid Description FINAL (RO) 8 most significant bits of the Default Value sts_sources_valid register. Bit 3 Bit 2 Bit 1 DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 SEC4 Bit No. [7:1] 0 Description Not used. SEC4 Bit indicating if SEC4 is valid. The input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. Bit Value 0 1 Value Description Input SEC4 is invalid. Input SEC4 is valid. Address (hex): 11 Register Name sts_reference_sources Inputs SEC1 & SEC2 Description (RO except for test when R/W) Reports any alarms active on inputs. Bit 3 Bit 2 Default Value 0110 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Address 11: Status of SEC2 Input Address 13: Status of SEC3 Input Out-of-band alarm (soft) Bit No. 7&3 Out-of-band alarm (hard) Description Out-of-band alarm (soft) Soft out-of-band alarm bit for input. A "soft" alarm will not invalidate an input. Out-of-band alarm (hard) Hard out-of-band alarm bit for input. A "hard" alarm will invalidate an input. No activity alarm Alarm indication from the activity monitors. Phase lock alarm If the DPLL can not indicate that it is phase locked onto the current source within 100 seconds this alarm will be raised. No activity alarm Phase lock alarm Out-of-band alarm (soft) Bit Value 0 1 Address 11: Status of SEC1 Input Address 14: Status of SEC4 Input Out-of band alarm (hard) No activity alarm Phase lock alarm Value Description No alarm. Alarm armed. Alarm thresholds set by Reg. 49 bits [7:4], or by Reg. 4A bits 7:4 if the input is currently selected. No alarm. Alarm armed. Alarm thresholds set by Reg. 49 bits [3:0], or by Reg. 4A bits [3:0] if the input is currently selected. No alarm. Input has an active no activity alarm. No alarm. Phase lock alarm. 6&2 0 1 5&1 4&0 0 1 0 1 Revision 5/November 2006 (c) Semtech Corp. Page 55 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL As Reg. 11, but for sts_reference_sources, Input SEC3 Address (hex): 13 As Reg. 11, but for sts_reference_sources, Input SEC4 Address (hex): 14 Address (hex): 19 Register Name cnfg_ref_selection_priority (SEC2 & SEC1) Description (R/W) Configures the relative Default Value priority of input sources SEC2 and *(TO) 0011 0010 SEC1. *(T4) 0011 0010 Bit 3 Bit 2 Bit 1 Bit 0 DATASHEET Default Value: 0110 0110 Default Value: 0110 0110 Bit 7 Bit 6 Bit 5 Bit 4 cnfg_ref_selection_priority_SEC2 Bit No. [7:4] Description cnfg_ref_selection_priority_SEC2 This 4-bit value represents the relative priority of input SEC2. The smaller the number, the higher the priority; zero disables the input. *When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the priority for the T0 path is configured. When this Bit 4 = 1 the priority for the T4 path is configured. cnfg_ref_selection_priority_SEC1 This 4-bit value represents the relative priority of input SEC1. The smaller the number, the higher the priority; zero disables the input. *When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the priority for the T0 path is configured. When this Bit 4 = 1 the priority for the T4 path is configured. Bit Value 0000 0001-1111 cnfg_ref_selection_priority_SEC1 Value Description Input SEC2 unavailable for automatic selection. Input SEC2 priority value. [3:0] 0000 0001-1111 Input SEC1 unavailable for automatic selection. Input SEC1 priority value. Revision 5/November 2006 (c) Semtech Corp. Page 56 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 1B Register Name cnfg_ref_selection_priority (SEC3) Description FINAL (R/W) Configures the relative priority of input source SEC3. DATASHEET Default Value *(T0) 0100 0000 *(T4) 0101 0100 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 cnfg_ref_selection_priority_SEC3 Bit No. [7:4] Description cnfg_ref_selection_priority_SEC3 This 4-bit value represents the relative priority of input SEC3. The smaller the number, the higher the priority; zero disables the input. *When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the priority for the T0 path is configured. When this Bit 4 = 1 the priority for the T4 path is configured. Not used. Bit Value 0000 0001-1111 Value Description Input SEC3 unavailable for automatic selection. Input SEC3 priority value. [3:0] - - Address (hex): 1C Register Name cnfg_ref_selection_priority (SEC4) Description (R/W) Configures the relative priority of input source SEC4. Default Value *(T0) 0000 0101 *(T4) 0000 0000 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 cnfg_ref_selection_priority_SEC4 Bit No. [7:4] [3:0] Description Not used. cnfg_ref_selection_priority_SEC4 This 4 bit value represents the relative priority of input SEC4. The smaller the number, the higher the priority; zero disables the input. *When Bit 4 (T4_T0_select) of Reg. 4B (cnfg_registers_source_select) = 0 the priority for the T0 path is configured. When this Bit 4 = 1 the priority for the T4 path is configured. Bit Value 0000 0001-1111 Value Description Input SEC4 unavailable for automatic selection. Input SEC4 priority value. Revision 5/November 2006 (c) Semtech Corp. Page 57 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 22 Use Register Name cnfg_ref_source_frequency Description SEC FINAL DATASHEET Bit 7 divn_SEC Bit 1 Bit 0 bucket_id_SEC reference_source_frequency_SEC 6 0 1 Input SEC [5:4] 00 01 10 11 Input SEC [3:0] reference_source_frequency_SEC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011-1111 Address (hex): 23 Address (hex): 27 Address (hex): 28 Use description for Reg. 22, but use Default Value: 0000 0000 Default Value: 0000 0011 Default Value: 0000 0011 Revision 5/November 2006 (c) Semtech Corp. Page 58 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 32 Register Name cnfg_operating_mode Description FINAL (R/W) Register to force the state of the TO DPLL controlling state machine. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 T0_DPLL_operating_mode Bit 0 Bit No. [7:3] [2:0] Description Not used. T0_DPLL_operating_mode This field is used to control the state of the internal finite state machine controlling the T0 DPLL. A value of zero is used to allow the finite state machine to control itself. Any other value will force the state machine to jump into that state. Care should be taken when forcing the state machine. Whilst it is forced, the internal monitoring functions cannot affect the internal state machine, therefore, the user is responsible for all monitoring and control functions required to achieve the desired functionality. Bit Value 000 001 010 011 100 101 110 111 Value Description Automatic (internal state machine controlled). Free Run. Holdover. Not used. Locked. Pre-locked2. Pre-locked. Phase Lost. Address (hex): 33 Register Name force_select_reference_source Description (R/W) Register used to force the Default Value selection of a particular reference source for the T0 DPLL. Bit 3 Bit 2 Bit 1 0000 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 forced_reference_source Bit No. [7:4] Description Not used. Bit Value Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 59 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 33 (cont...) Register Name force_select_reference_source Description FINAL (R/W) Register used to force the Default Value selection of a particular reference source for the T0 DPLL. Bit 3 Bit 2 Bit 1 DATASHEET 0000 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 forced_reference_source Bit No. [3:0] Description forced_reference_source Value representing the source to be selected by the T0 DPLL. Value of 0 hex will leave the selection to the automatic control mechanism within the device. Using this mechanism will bypass all the monitoring functions assuming the selected input to be valid. If the device is not in state "Locked" then it will progress to state locked in the usual manner. If the input fails, the device will not change state to Holdover, as it is not allowed to disqualify the source. The effect of this register is simply to raise the priority of the selected input reference to "1" (highest). To ensure selection of the programmed input reference under all circumstances, Revertive mode should be enabled (Reg. 34 Bit 0 set to "1"). Bit Value 0000 0011 0100 1000 1001 1111 All other values Value Description Automatic state machine source selection T0 DPLL forced to select input SEC1. T0 DPLL forced to select input SEC2. T0 DPLL forced to select input SEC3. T0 DPLL forced to select input SEC4. Automatic. Not used. Address (hex): 34 Register Name cnfg_input_mode Description (R/W) Register controlling various Default Value input modes of the device. Bit 3 extsync_en Bit 2 ip_sonsdhb Bit 1 1100 1010 Bit 7 Set to 0 Bit 6 phalarm_timeout Description Set to 0. Bit 5 XO_edge Bit 4 man_holdover Bit 0 reversion_mode Bit No. 7 6 Bit Value 0 0 1 Value Description Set to 0. Phase alarms on sources only cancelled by software. Phase alarms on sources automatically time out. phalarm_timeout Bit to enable the automatic timeout facility on phase alarms. When enabled, any source with a phase alarm set will have its phase alarm cancelled after 128 seconds. XO_edge If the 12.800 MHz oscillator module connected to REFCLK has one edge faster than the other, then for jitter performance reasons, the faster edge should be selected. This bit allows either the rising edge or the falling edge to be selected. 5 0 1 Device uses the rising edge of the external oscillator. Device uses the falling edge of the external oscillator. Revision 5/November 2006 (c) Semtech Corp. Page 60 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 34 (cont...) Register Name cnfg_input_mode Description FINAL (R/W) Register controlling various Default Value input modes of the device. Bit 3 extsync_en Bit 2 ip_sonsdhb Bit 1 DATASHEET 1100 1010 Bit 7 Set to 0 Bit 6 phalarm_timeout Description Bit 5 XO_edge Bit 4 man_holdover Bit 0 reversion_mode Bit No. 4 Bit Value 0 1 Value Description Holdover frequency is determined automatically. Holdover frequency is taken from cnfg_holdover_frequency register. man_holdover Bit to select whether or not the Holdover frequency is taken directly from Reg. 3E/Reg. 3F/Reg. 40 (cnfg_holdover_frequency). If this bit is set then it overrides any other Holdover control bits. extsync_en Bit to select whether or not the T0 DPLL will look for a reference Sync pulse on the SYNC2K input pin. Even though this bit may enable the external Sync reference, it may be disabled according to auto_extsync_en. ip_sonsdhb Bit to configure input frequencies to be either SONET or SDH derived. This applies only to selections of 0001 (bin) in the cnfg_ref_source_frequency registers when the input frequency is either 1544 kHz or 2048 kHz. Not used. reversion_mode Bit to select Revertive/Non-revertive mode. When in Non-revertive mode, the device will not automatically switch to a higher priority source, unless the current source fails. When in Revertive mode the device will always select the highest priority source. 3 0 1 No external Sync signal- SYNC2K pin ignored. External Sync derived from SYNC2K pin according to auto_extsync_en. 2 0 1 SDH- inputs set to 0001 expected to be 2048 kHz. SONET- inputs set to 0001 expected to be 1544 kHz. 1 0 0 1 Non-revertive mode. Revertive mode. Revision 5/November 2006 (c) Semtech Corp. Page 61 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 35 Register Name cnfg_T4_path Description FINAL Register to configure the inputs Default Value and other features in the T4 path. Bit 3 Bit 2 Bit 1 DATASHEET 0100 0000 Bit 7 lock_T4_to_T0 Bit 6 T4_dig_feedback Description Bit 5 Bit 4 Bit 0 T4_forced_reference_source Bit No. 7 Bit Value 0 1 Value Description T4 path locks independently from the T0 path. T4 DPLL locks to the output of the T0 DPLL. lock_T4_to_T0 Bit selects either the T4 direct inputs, or T0 DPLL as the input of the T4 path. This allows the T4 DPLL to be used to produce different sets of frequencies to the T0 DPLL but still maintain lock. T4_dig_feedback Bit to select digital feedback mode for the T4 DPLL. Not used. T4_forced_reference_source This field can be used to force the T4 DPLL to select a particular input. A value of zero in this field allows the T4 input to be selected automatically via the priority and input monitoring functions. 6 [5:4] [3:0] 0 1 0000 0011 0100 1000 1001 All other values T4 DPLL in analog feedback mode. T4 DPLL in digital feedback mode. T4 DPLL automatic source selection. T4 DPLL forced to select input SEC1. T4 DPLL forced to select input SEC2. T4 DPLL forced to select input SEC3. T4 DPLL forced to select input SEC4. Not used. Address (hex): 38 Register Name cnfg_dig_outputs_sonsdh Description Configures Digital1 and Digital2 output frequencies to be SONET or SDH compatible frequencies. Bit 3 Bit 2 Default Value 0000 1101* Bit 7 Bit 6 dig2_sonsdh Bit 5 dig1_sonsdh Bit 4 Bit 1 Bit 0 Bit No. 7 6 Description Not used. dig2_sonsdh Selects whether the frequencies generated by the Digital2 frequency generator are SONET derived or SDH. *Default value of this bit is set by the SONSDHB pin at power-up. Bit Value 1 0 Value Description Digital2 can be selected from 1544/3088/6176/ 12352 kHz. Digital2 can be selected from 2048/4096/8192/ 16384 kHz. Revision 5/November 2006 (c) Semtech Corp. Page 62 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 38 (cont...) Register Name cnfg_dig_outputs_sonsdh Description FINAL Configures Digital1 and Digital2 output frequencies to be SONET or SDH compatible frequencies. Bit 3 Bit 2 Default Value DATASHEET 0000 1101* Bit 7 Bit 6 dig2_sonsdh Bit 5 dig1_sonsdh Bit 4 Bit 1 Bit 0 Bit No. 5 Description dig1_sonsdh Selects whether the frequencies generated by the Digital1 frequency generator are SONET derived or SDH. *Default value of this bit is set by the SONSDHB pin at power-up. Not used. Bit Value 1 0 Value Description Digital1 can be selected from 1544/3088/6176/ 12352 kHz. Digital1 can be selected from 2048/4096/8192/ 16384 kHz. [4:0] - - Address (hex): 39 Register Name cnfg_digtial_frequencies Description (R/W) Configures the actual Default Value frequencies of Digital1 & Digital2. Bit 3 Bit 2 Bit 1 0000 1000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 digital2_frequency Bit No. [7:6] Description digital1_frequency Bit Value 00 01 10 11 00 01 10 11 Value Description Digital2 set to 1544 kHz or 2048 kHz. Digital2 set to 3088 kHz or 4096 kHz. Digital2 set to 6176 kHz or 8192 kHz. Digital2 set to 12353 kHz or 16384 kHz. Digital1 set to 1544 kHz or 2048 kHz. Digital1 set to 3088 kHz or 4096 kHz. Digital1 set to 6176 kHz or 8192 kHz. Digital1 set to 12353 kHz or 16384 kHz. digital2_frequency Configures the frequency of Digital2. Whether this is SONET or SDH based is configured by Bit 6 (dig2_sonsdh) of Reg. 38. digital1_frequency Configures the frequency of Digital1. Whether this is SONET or SDH based is configured by Bit 5 (dig1_sonsdh) of Reg. 38. Not used. [5:4] [3:0] Revision 5/November 2006 (c) Semtech Corp. Page 63 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 3A Register Name cnfg_differential_outputs Description FINAL (R/W) Configures the electrical Default Value compatibility of the differential output driver O1 to be 3 V PECL or 3 V LVDS. Bit 3 Bit 2 Bit 1 DATASHEET 1100 0010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 O1_LVDS_PECL Bit No. [7:2] [1:0] Description Not used. O1_LVDS_PECL Selection of the electrical compatibility of Output O1 between 3 V PECL and 3 V LVDS. Bit Value 00 01 10 11 Value Description Output O1 disabled. Output O1 3 V PECL compatible. Output O1 3 V LVDS compatible. Not used. Address (hex): 3B Register Name cnfg_auto_bw_sel Description (R/W) Register to select Default Value automatic bandwidth selection for the T0 DPLL path Bit 3 T0_lim_int Description auto_BW_sel Bit to select locked bandwidth (Reg. 67) or acquisition bandwidth (Reg. 69) for the T0 DPLL. Not used. T0_lim_int When set to 1 the integral path value of the DPLL is limited or frozen when the DPLL reaches either min. or max. frequency. This can be used to minimize subsequent overshoot when the DPLL is pulling in. Note that when this happens, the reported frequency value via current_DPLL_freq (Reg. 0C, 0D and 07) is also frozen. Not used. Bit Value 1 0 1 0 Value Description Automatically selects either locked or acquisition bandwidth as appropriate. Always selects locked bandwidth. DPLL value frozen. DPLL not frozen. Bit 2 Bit 1 1111 1101 Bit 7 auto_BW_sel Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 0 [6:4] 3 [2:0] - - Revision 5/November 2006 (c) Semtech Corp. Page 64 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 3C Register Name cnfg_nominal_frequency [7:0] Description FINAL (R/W) Bits [7:0] of the register used to calibrate the crystal oscillator used to clock the device. Bit 3 Bit 2 Default Value DATASHEET 1001 1001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 cnfg_nominal_frequency_value[7:0] Bit No. [7:0] Description cnfg_nominal_frequency_value[7:0] Bit Value Value Description See register description of Reg. 3D (cnfg_nominal_frequency_value[15:8]). Address (hex): 3D Register Name cnfg_nominal_frequency [15:8] Description (R/W) Bits [15:8] of the register used to calibrate the crystal oscillator used to clock the device. Bit 3 Bit 2 Default Value 1001 1001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 cnfg_nominal_frequency_value[15:8] Bit No. [7:0] Description cnfg_nominal_frequency_value[15:8] This register is used in conjunction with Reg. 3C (cnfg_nominal_frequency_value[7:0]) to be able to offset the frequency of the crystal oscillator by up to +514 ppm and -771 ppm. The default value represents 0 ppm offset from 12.800 MHz. This value is an unsigned integer. Bit Value Value Description In order to program the ppm offset of the crystal oscillator frequency, the value in Reg. 3C and Reg. 3D hex need to be concatenated. This value is an unsigned integer. The value multiplied by 0.0196229 dec. will give the value in ppm. To calculate the absolute value, the default 39321 (9999 hex) needs to be subtracted. Address (hex): 3E Register Name cnfg_holdover_frequency [7:0] Bit 6 Bit 5 Description (R/W) Bits [7:0] of the manual Holdover frequency register. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 holdover_frequency_value[7:0] Bit No. [7:0] Description holdover_frequency_value[7:0] Bit Value Value Description See Reg. 3F (cnfg_holdover_frequency) for details. Revision 5/November 2006 (c) Semtech Corp. Page 65 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 3F Register Name cnfg_holdover_frequency [15:8] Bit 6 Bit 5 Description FINAL (R/W) Bits [15:8] of the manual Holdover frequency register. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 holdover_frequency_value[15:8] Bit No. [7:0] Description holdover_frequency_value[15:8] This value in this register is combined with the value in Reg. 3E and Bits [2:0] of Reg. 40 to represent the programmed Holdover frequency of the T0 DPLL. This register is designed such that software can read the sts_current_DPLL_frequency register (Reg. 0C, Reg. 0D and Reg. 07) and filter the value. The result will then be in a suitable format to simply write back to the cnfg_holdover_frequency register. This register can be programmed to read back the internally averaged Holdover frequency rather than the programmed value, see Bit 5 of Reg. 40 cnfg_holdover_modes. Bit Value Value Description In order to calculate the Holdover ppm offset of the DPLL with respect to the crystal oscillator frequency, the value in Reg. 3E and the value in Bits [2:0] of Reg. 40 need to be concatenated. This value is a 2's complement signed integer. The value multiplied by 0.0003068 dec. will give the value in ppm. Address (hex): 40 Register Name cnfg_holdover_modes Description (R/W) Register to control the Holdover modes of the T0 DPLL. Bit 3 Bit 2 Default Value 1000 1000 Bit 7 Bit 6 Bit 5 read_average Bit 4 Bit 1 Bit 0 auto_averaging fast_averaging Bit No. 7 Description mini_holdover_mode Bit Value 0 1 holdover_frequency_value [18:16] Value Description Averaged frequency not used, Holdover frequency either manual or instantaneously frozen. Averaged frequency used, providing manual Holdover mode is not engaged. Slow Holdover frequency averaging enabled. Fast Holdover frequency averaging enabled. auto_averaging Bit to enable the use of the averaged frequency value during Holdover. This bit is overridden by the manual Holdover control (Bit 4, man_holdover, in Reg. 34). fast_averaging Bit to control the rate of averaging of the Holdover frequency. Fast averaging gives a -3db response point of approximately 8 minutes. Slow averaging give a -3db response point of approximately 110 minutes. 6 0 1 Revision 5/November 2006 (c) Semtech Corp. Page 66 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 40 (cont...) Register Name cnfg_holdover_modes Description FINAL (R/W) Register to control the Holdover modes of the T0 DPLL. Bit 3 Bit 2 Default Value DATASHEET 1000 1000 Bit 7 Bit 6 Bit 5 read_average Bit 4 Bit 1 Bit 0 auto_averaging fast_averaging Bit No. 5 Description mini_holdover_mode Bit Value 0 1 holdover_frequency_value [18:16] Value Description Value read from holdover_frequency_value is the value written to it. Value read from a holdover_frequency_value is either the fast or slow averaged frequency as determined by fast_averaging. read_average Bit to control whether the value read from the holdover_frequency_value register is the value written to that register, or the averaged Holdover frequency. This allows software to use the internal averager as part of the Holdover algorithm, but use manual Holdover mode plus software to enhance the performance. mini_holdover_mode Mini-holdover is a term used to describe the state of the DPLL when it is in locked mode, but it has temporarily lost its input. This may be a temporary state, or last for many seconds whilst an input is checked for inactivity. The DPLL behaves exactly as in Holdover, and the frequency can be determined in the same selection of ways (instantaneously, fast averaged or slow averaged). holdover_frequency_value [18:16] [4:3] 00 01 10 11 Mini-holdover frequency determined in the same way as for full Holdover mode. Mini-holdover frequency frozen instantaneously. Mini-holdover frequency taken from fast averager. Mini-holdover frequency taken from slow averager. [2:0] - See Reg. 3F (cnfg_holdover_frequency) for details. Revision 5/November 2006 (c) Semtech Corp. Page 67 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 41 Register Name cnfg_DPLL_freq_limit [7:0] Bit 6 Bit 5 Description FINAL (R/W) Bits [7:0] of the DPLL frequency limit register. Bit 3 Bit 2 Default Value DATASHEET 0111 0110 Bit 7 Bit 4 Bit 1 Bit 0 DPLL_freq_limit_value[7:0] Bit No. [7:0] Description DPLL_freq_limit_value[7:0] This register defines the extent of frequency offset to which either the T0 or the T4 DPLL will track a source before limiting- i.e. it represents the pull-in range of the DPLLs. The offset of the device is determined by the frequency offset of the DPLL when compared to the offset of the external crystal oscillator clocking the device. If the oscillator is calibrated using cnfg_nominal_frequency Reg. 3C and 3D, then this calibration is automatically taken into account. The DPLL frequency limit limits the offset of the DPLL when compared to the calibrated oscillator frequency. Bit Value Value Description In order to calculate the frequency limit in ppm, Bits [1:0] of Reg. 42 and Bits [7:0] of Reg. 41 need to be concatenated. This value is a unsigned integer and represents limit both positive and negative in ppm. The value multiplied by 0.078 will give the value in ppm. Address (hex): 42 Register Name cnfg_DPLL_freq_limit [9:8] Bit 6 Bit 5 Description (R/W) Bits [9:8] of the DPLL frequency limit register. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 DPLL_freq_limit_value[9:8] Bit No. [7:2] [1:0] Description Not used. DPLL_freq_limit_value[9:8] Bit Value Value Description See Reg. 41 (cnfg_DPLL_freq_limit) for details. Revision 5/November 2006 (c) Semtech Corp. Page 68 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 43 Register Name cnfg_interrupt_mask [7:0] Bit 6 Bit 5 Description FINAL (R/W) Bits [7:0] of the interrupt mask register. Bit 3 SEC2 interrupt not masked Bit 2 SEC1 interrupt not masked Value Description Default Value DATASHEET 0000 0000 Bit 7 SEC3 interrupt not masked Bit No. 7 [7:2] 3 2 [1:0] Bit 4 Bit 1 Bit 0 Description SEC3 interrupt not masked Mask bit for input SEC3 interrupt. Not used. SEC2 interrupt not masked Mask bit for input SEC2 interrupt. SEC1 interrupt not masked Mask bit for input SEC1 interrupt. Not used. Bit Value 0 1 0 1 0 1 - Input SEC3 cannot generate interrupts. Input SEC3 can generate interrupts. Input SEC2 cannot generate interrupts. Input SEC2 can generate interrupts. Input SEC1 cannot generate interrupts. Input SEC1 can generate interrupts. - Address (hex): 44 Register Name cnfg_interrupt_mask [15:8] Bit 6 main_ref_failed interrupt not masked Description operating_mode interrupt not masked Mask bit for operating_mode interrupt. main_ref_failed interrupt not masked Mask bit for main_ref_failed interrupt. Not used. SEC4 interrupt not masked Mask bit for input SEC4 interrupt. Bit Value 0 1 0 1 0 1 Value Description Operating mode cannot generate interrupts. Operating mode can generate interrupts. Main reference failure cannot generate interrupts. Main reference failure can generate interrupts. Input SEC4 cannot generate interrupts. Input SEC4 can generate interrupts. Bit 5 Description (R/W) Bits [15:8] of the interrupt mask register. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 operating_ mode interrupt not masked Bit No. 7 6 [5:1] 0 Bit 4 Bit 1 Bit 0 SEC4 interrupt not masked Revision 5/November 2006 (c) Semtech Corp. Page 69 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 45 Register Name cnfg_interrupt_mask [23:16] Bit 6 T4_status interrupt not masked Bit No. 7 6 [5:0] Description Not used. T4_status Mask bit for T4_status interrupt. Not used. Bit Value 0 1 Value Description Change in T4 status cannot generate interrupts. Change in T4 status can generate interrupts. Bit 5 Description FINAL (R/W) Bits [23:16] of the interrupt Default Value mask register. Bit 3 Bit 2 Bit 1 DATASHEET 0000 0000 Bit 7 Bit 4 Bit 0 Address (hex): 46 Register Name cnfg_freq_divn [7:0] Description (R/W) Bits [7:0] of the division factor for inputs using the DivN feature. Bit 3 Bit 2 Default Value 1111 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 divn_value[7:0] Bit No. [7:0] Description divn_value[7:0] Bit Value Value Description See Reg. 47 (cnfg_freq_divn) for details. Address (hex): 47 Register Name cnfg_freq_divn [13:8] Description (R/W) Bits [13:8] of the division factor for inputs using the DivN feature. Bit 3 Bit 2 Default Value 0011 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 divn_value[13:8] Bit No. [7:6] Description Not used. Bit Value Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 70 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 47 (cont...) Register Name cnfg_freq_divn [13:8] Description FINAL (R/W) Bits [13:8] of the division factor for inputs using the DivN feature. Bit 3 Bit 2 Default Value DATASHEET 0011 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 divn_value[13:8] Bit No. [5:0] Description divn_value[13:8] This register, in conjunction with Reg. 46 (cnfg_freq_divn) represents the integer value by which to divide inputs that use the DivN pre-divider. The divn feature supports input frequencies up to a maximum of 100 MHz; therefore, the maximum value that should be written to this register is 30D3 hex (12499 dec.). Use of higher DivN values may result in unreliable behavior. Bit Value Value Description The input frequency will be divided by the value in this register plus 1. i.e. to divide by 8, program a value of 7. Address (hex): 48 Register Name cnfg_monitors Description (R/W) Configuration register Default Value controlling several input monitoring and switching options. Bit 3 PBO_freeze Bit 2 PBO_en Bit 1 freq_monitor_ soft_enable 0000 0101* Bit 7 freq_mon_clk Bit 6 los_flag_on_ TDO Description Bit 5 ultra_fast_ switch Bit 4 ext_switch Bit 0 freq_monitor_ hard_enable Bit No. 7 Bit Value 0 1 Value Description Frequency monitors clocked by output of TO DPLL. Frequency monitors clocked by crystal oscillator frequency. Normal mode, TDO complies with IEEE 1149.1. TDO pin used to indicate the state of the main_ref_fail interrupt status. This allows a system to have a hardware indication of a source failure very rapidly. freq_mon_clk Bit to select the source of the clock to the frequency monitors to be either from the output clock or directly from the crystal oscillator. los_flag_on_TDO Bit to select whether the main_ref_fail interrupt from the T0 DPLL is flagged on the TDO pin. If enabled this will not strictly conform to the IEEE 1149.1 JTAG standard for the function of the TDO pin. When enabled the TDO pin will simply mimic the state of the main_ref_fail interrupt status bit. ultra_fast_switch Bit to enable ultra-fast switching mode. When in this mode, the device will disqualify a locked-to source as soon as it detects a few missing input cycles. 6 0 1 5 0 1 Currently selected source only disqualified by Leaky Bucket or frequency monitors. Currently selected source disqualified after less than 3 missing input cycles. Revision 5/November 2006 (c) Semtech Corp. Page 71 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 48 (cont...) Register Name cnfg_monitors Description FINAL (R/W) Configuration register Default Value controlling several input monitoring and switching options. Bit 3 PBO_freeze Bit 2 PBO_en Bit 1 freq_monitor_ soft_enable DATASHEET 0000 0101* Bit 7 freq_mon_clk Bit 6 los_flag_on_ TDO Description Bit 5 ultra_fast_ switch Bit 4 ext_switch Bit 0 freq_monitor_ hard_enable Bit No. 4 Bit Value 0 1 Value Description Normal operation mode. External source switching mode enabled. Operating mode of the device is always forced to be "locked" when in this mode. ext_switch Bit to enable external switching mode. When in external switching mode, the device is only allowed to lock to a pair of sources. If the SRCSW pin is High, the device will be forced to lock to input SEC1 regardless of the signal present on that input. If the SRCSW pin is Low, the device will be forced to lock to input SEC2 regardless of the signal present on that input. * The default value of this bit is dependent on the value of the SRCSW pin at power-up. PBO_freeze Bit to control the freezing of Phase Build-out operation. If Phase Build-out has been enabled and there have been some source switches, then the input-output phase relationship of the T0 DPLL is unknown. If Phase Build-out is no longer required, then it can be frozen. This will maintain the current input-output phase relationship, but not allow further Phase Build-out events to take place. Simply disabling Phase Build-out could cause a phase shift in the output, as the T0 DPLL re-locks the phase to zero degrees. PBO_en Bit to enable Phase Build-out events on source switching. When enabled a Phase Build-out event is triggered every time the T0 DPLL selects a new source- this includes exiting the Holdover or Freerun states. freq_monitor_soft_enable Control to enable frequency monitoring of input reference sources using soft frequency alarms. freq_monitor_hard_enable Control to enable frequency monitoring of input reference sources using hard frequency alarms. 3 0 1 Phase Build-out not frozen. Phase Build-out frozen, no further Phase Build-out events will occur. 2 0 1 Phase Build-out not enabled. T0 DPLL locks to zero degrees phase. Phase Build-out enabled on source switching. 1 0 1 0 1 Soft frequency monitor alarms disabled. Soft frequency monitor alarms enabled. Hard frequency monitor alarms disabled. Hard frequency monitor alarms enabled. 0 Revision 5/November 2006 (c) Semtech Corp. Page 72 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 49 Register Name cnfg_freq_mon_threshold Description FINAL (R/W) Register to set both the hard and soft frequency alarm limits for the monitors on the input reference sources. Bit 3 Bit 2 Default Value DATASHEET 0010 0011 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 soft_frequency_alarm_threshold Bit No. [7:4] Description soft_frequency_alarm_threshold Threshold to trigger the soft frequency alarms in the sts_reference_sources registers. This is only used for monitoring. hard_frequency_alarm_threshold Threshold to trigger the hard frequency alarms in the sts_reference_sources registers, which can cause a reference source rejection. Bit Value - hard_frequency_alarm_threshold Value Description To calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. The limit is symmetrical about zero. A value of 0010 bin corresponds to an alarm limit of 11.43 ppm. To calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. The limit is symmetrical about zero. A value of 0011 bin corresponds to an alarm limit of 15.24 ppm. [3:0] Address (hex): 4A Register Name cnfg_current_freq_mon_ threshold Description (R/W) Register to set both the hard and soft frequency alarm limits for the monitors on the currently selected reference source. Bit 3 Bit 2 Default Value 0010 0011 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 current_soft_frequency_alarm_threshold Bit No. [7:4] Description current_soft_frequency_alarm_threshold Threshold to trigger the soft frequency alarm in the sts_reference_sources register applying to the currently selected source.The currently selected source can be monitored for frequency using different limits to all other sources. current_hard_frequency_alarm_threshold Threshold to trigger the hard frequency alarm in the sts_reference_sources register applying to the currently selected source. Bit Value - current_hard_frequency_alarm_threshold Value Description To calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. The limit is symmetrical about zero. A value of 0010 bin corresponds to an alarm limit of 11.43 ppm. [3:0] To calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. The limit is symmetrical about zero. A value of 0011 bin corresponds to an alarm limit of 15.24 ppm. Revision 5/November 2006 (c) Semtech Corp. Page 73 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 4B Register Name cnfg_registers_source_select Description FINAL (R/W) Register to select the source of many of the registers. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 T4_T0_select Bit 1 Bit 0 frequency_measurement_channel_select Bit Value 0 1 Value Description T0 path registers selected. T4 path registers selected. Bit No. [7:5] 4 Description Not used. T4_T0_select Bit to select between the T0 and T4 path for: Reg. 0A, 0B (sts_priority_table) Reg. 0C, 0D and 07 (sts_current_DPLL_frequency) Reg. 77, 78 (sts_current_phase) frequency_measurement_channel_select Register to select which input channel the frequency measurement result in Reg. 4C (sts_freq_measurement) is taken from. [3:0] 0011 0111 1000 1001 All other values Frequency measurement taken from input SEC1. Frequency measurement taken from input SEC2. Frequency measurement taken from input SEC3. Frequency measurement taken from input SEC4. Not used- refers to no input channel. Address (hex): 4C Register Name sts_freq_measurement Description (RO) Register from which the frequency measurement result can be read. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 freq_measurement_value Bit No. [7:0] Description freq_measurement_value This represents the value of the frequency measurement on the channel number selected in Reg. 4B (cnfg_registers_source_select). This value will represent the offset in frequency from the clock to the frequency monitors. This can be either the crystal oscillator to the device, or the output of the T0 DPLL as selected in Reg. 48 Bit 7 cnfg_monitors. Bit Value Value Description This is an 8-bit 2's complement signed integer. To calculate the offset in ppm of the selected input channel, this value should be multiplied by 3.81 ppm. Revision 5/November 2006 (c) Semtech Corp. Page 74 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 4D Register Name cnfg_DPLL_soft_limit Description FINAL (R/W) Register to program the Default Value soft frequency limit of the two DPLLs. Exceeding this limit will have no effect beyond triggering a flag. Bit 3 DPLL_soft_limit_value Bit 2 Bit 1 DATASHEET 1000 1110 Bit 7 freq_lim_ph_ loss Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 0 Description freq_lim_ph_loss Bit to enable the phase lost indication when the DPLL hits its hard frequency limit as programmed in Reg. 41 and Reg. 42 (cnfg_DPLL_freq_limit). This results in the DPLL entering the phase lost state any time the DPLL tracks to the extent of its hard limit. DPLL_soft_limit_value Register to program to what extent either of the DPLLs tracks a source before raising its soft frequency alarm flag (Bits 5 and 4 of Reg. 09, sts_operating). This offset is compared to the crystal oscillator frequency taking into account any programmed calibration. Bit Value 0 1 Value Description Phase lost/locked determined normally. Phase lost forced when DPLL tracks to hard limit. [6:0] - To calculate the ppm offset multiply this 7-bit value by 0.628 ppm. The limit is symmetrical about zero. A value of 0001110 bin is equivalent to 8.79 ppm. Address (hex): 50 Register Name cnfg_upper_threshold_0 Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 0. Bit 3 Bit 2 Default Value 0000 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration upper_threshold_0_value Bit No. [7:0] Description upper_threshold_0_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 53 (cnfg_decay_rate_0), in which this does not occur, the accumulator is decremented by 1. When the accumulator count reaches the value programmed as the upper_threshold_0_value, the Leaky Bucket raises an input inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will raise an inactivity alarm. Revision 5/November 2006 (c) Semtech Corp. Page 75 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 51 Register Name cnfg_lower_threshold_0 Description FINAL (R/W) Register to program the activity alarm resetting limit for Leaky Bucket Configuration 0. Bit 3 Bit 2 Default Value DATASHEET 0000 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration lower_threshold_0_value Bit No. [7:0] Description lower_threshold_0_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 53 (cnfg_decay_rate_0), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_0_value is the value at which the Leaky Bucket will reset an inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will reset an inactivity alarm. Address (hex): 52 Register Name cnfg_bucket_size_0 Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 0. Bit 3 Bit 2 Default Value 0000 1000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration bucket_size_0_value Bit No. [7:0] Description bucket_size_0_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 53 (cnfg_decay_rate_0), in which this does not occur, the accumulator is decremented by 1. The number in the Bucket cannot exceed the value programmed into this register. Bit Value Value Description Value at which the Leaky Bucket will stop incrementing, even with further inactive periods. Revision 5/November 2006 (c) Semtech Corp. Page 76 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 53 Register Name cnfg_decay_rate_0 Description FINAL (R/W) Register to program the "decay" or "leak" rate for Leaky Bucket Configuration 0. Bit 3 Bit 2 Default Value DATASHEET 0000 0001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration decay_rate_0_value Bit No. [7:2] [1:0] Description Not used. decay_rate_0_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. The Leaky Bucket can be programmed to "leak" or "decay" at the same rate as the "fill" cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Bit Value 00 01 10 11 Value Description Bucket decay rate of 1 every 128 ms. Bucket decay rate of 1 every 256 ms. Bucket decay rate of 1 every 512 ms. Bucket decay rate of 1 every 1024 ms. Address (hex): 54 Register Name cnfg_upper_threshold_1 Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 1. Bit 3 Bit 2 Default Value 0000 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration upper_threshold_1_value Bit No. [7:0] Description upper_threshold_1_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 57 (cnfg_decay_rate_1), in which this does not occur, the accumulator is decremented by 1. When the accumulator count reaches the value programmed as the upper_threshold_1_value, the Leaky Bucket raises an input inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will raise an inactivity alarm. Revision 5/November 2006 (c) Semtech Corp. Page 77 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 55 Register Name cnfg_lower_threshold_1 Description FINAL (R/W) Register to program the activity alarm resetting limit for Leaky Bucket Configuration 1. Bit 3 Bit 2 Default Value DATASHEET 0000 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration lower_threshold_1_value Bit No. [7:0] Description lower_threshold_1_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 57 (cnfg_decay_rate_1), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_1_value is the value at which the Leaky Bucket will reset an inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will reset an inactivity alarm. Address (hex): 56 Register Name cnfg_bucket_size_1 Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 1. Bit 3 Bit 2 Default Value 0000 1000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration bucket_size_1_value Bit No. [7:0] Description bucket_size_1_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 57 (cnfg_decay_rate_1), in which this does not occur, the accumulator is decremented by 1. The number in the Bucket cannot exceed the value programmed into this register. Bit Value Value Description Value at which the Leaky Bucket will stop incrementing, even with further inactive periods. Revision 5/November 2006 (c) Semtech Corp. Page 78 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 57 Register Name cnfg_decay_rate_1 Description FINAL (R/W) Register to program the "decay" or "leak" rate for Leaky Bucket Configuration 1. Bit 3 Bit 2 Default Value DATASHEET 0000 0001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration decay_rate_1_value Bit No. [7:2] [1:0] Description Not used. decay_rate_1_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. The Leaky Bucket can be programmed to "leak" or "decay" at the same rate as the "fill" cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Bit Value 00 01 10 11 Value Description Bucket decay rate of 1 every 128 ms. Bucket decay rate of 1 every 256 ms. Bucket decay rate of 1 every 512 ms. Bucket decay rate of 1 every 1024 ms. Address (hex): 58 Register Name cnfg_upper_threshold_2 Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 2. Bit 3 Bit 2 Default Value 0000 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration upper_threshold_2_value Bit No. [7:0] Description upper_threshold_2_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 5B (cnfg_decay_rate_2), in which this does not occur, the accumulator is decremented by 1. When the accumulator count reaches the value programmed as the upper_threshold_2_value, the Leaky Bucket raises an input inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will raise an inactivity alarm. Revision 5/November 2006 (c) Semtech Corp. Page 79 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 59 Register Name cnfg_lower_threshold_2 Description FINAL (R/W) Register to program the activity alarm resetting limit for Leaky Bucket Configuration 2. Bit 3 Bit 2 Default Value DATASHEET 0000 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration lower_threshold_2_value Bit No. [7:0] Description lower_threshold_2_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 5B (cnfg_decay_rate_2), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_2_value is the value at which the Leaky Bucket will reset an inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will reset an inactivity alarm. Address (hex): 5A Register Name cnfg_bucket_size_2 Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 2. Bit 3 Bit 2 Default Value 0000 1000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration bucket_size_2_value Bit No. [7:0] Description bucket_size_2_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 5B (cnfg_decay_rate_2), in which this does not occur, the accumulator is decremented by 1. The number in the Bucket cannot exceed the value programmed into this register. Bit Value Value Description Value at which the Leaky Bucket will stop incrementing, even with further inactive periods. Revision 5/November 2006 (c) Semtech Corp. Page 80 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 5B Register Name cnfg_decay_rate_2 Description FINAL (R/W) Register to program the "decay" or "leak" rate for Leaky Bucket Configuration 2. Bit 3 Bit 2 Default Value DATASHEET 0000 0001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration decay_rate_2_value Bit No. [7:2] [1:0] Description Not used. decay_rate_2_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. The Leaky Bucket can be programmed to "leak" or "decay" at the same rate as the "fill" cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Bit Value 00 01 10 11 Value Description Bucket decay rate of 1 every 128 ms. Bucket decay rate of 1 every 256 ms. Bucket decay rate of 1 every 512 ms. Bucket decay rate of 1 every 1024 ms. Address (hex): 5C Register Name cnfg_upper_threshold_3 Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 3. Bit 3 Bit 2 Default Value 0000 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration upper_threshold_3_value Bit No. [7:0] Description upper_threshold_3_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 5F (cnfg_decay_rate_3), in which this does not occur, the accumulator is decremented by 1. When the accumulator count reaches the value programmed as the upper_threshold_3_value, the Leaky Bucket raises an input inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will raise an inactivity alarm. Revision 5/November 2006 (c) Semtech Corp. Page 81 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 5D Register Name cnfg_lower_threshold_3 Description FINAL (R/W) Register to program the activity alarm resetting limit for Leaky Bucket Configuration 3. Bit 3 Bit 2 Default Value DATASHEET 0000 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration lower_threshold_3_value Bit No. [7:0] Description lower_threshold_3_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 5F (cnfg_decay_rate_3), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_3_value is the value at which the Leaky Bucket will reset an inactivity alarm. Bit Value Value Description Value at which the Leaky Bucket will reset an inactivity alarm. Address (hex): 5E Register Name cnfg_bucket_size_3 Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 3. Bit 3 Bit 2 Default Value 0000 1000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration bucket_size_3_value Bit No. [7:0] Description bucket_size_3_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in Reg. 5F (cnfg_decay_rate_3), in which this does not occur, the accumulator is decremented by 1. The number in the Bucket cannot exceed the value programmed into this register. Bit Value Value Description Value at which the Leaky Bucket will stop incrementing, even with further inactive periods. Revision 5/November 2006 (c) Semtech Corp. Page 82 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 5F Register Name cnfg_decay_rate_3 Description FINAL (R/W) Register to program the "decay" or "leak" rate for Leaky Bucket Configuration 3. Bit 3 Bit 2 Default Value DATASHEET 0000 0001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Leaky Bucket Configuration decay_rate_3_value Bit No. [7:2] [1:0] Description Not used. decay_rate_3_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. The Leaky Bucket can be programmed to "leak" or "decay" at the same rate as the "fill" cycle, or effectively at one half, one quarter, or one eighth of the fill rate. 00 01 10 11 Bit Value Value Description Bucket decay rate of 1 every 128 ms. Bucket decay rate of 1 every 256 ms. Bucket decay rate of 1 every 512 ms. Bucket decay rate of 1 every 1024 ms. Revision 5/November 2006 (c) Semtech Corp. Page 83 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 60 Register Name cnfg_output_frequency (O2) Description FINAL (R/W) Register to configure and enable the frequencies available on output O2. Bit 3 Bit 2 Default Value DATASHEET 1000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 output_freq_O2 Bit No. [7:4] Description output_freq_O2 Configuration of the output frequency available at output O2. Many of the frequencies available are dependent on the frequencies of the T0 APLL and the T4 APLL. These are configured in Reg. 64 and Reg. 65. For more detail see the detailed section on configuring the output frequencies. Bit Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Value Description Output disabled. 2 kHz. 8 kHz. Digital2 (Reg. 39 cnfg_digital_frequencies). Digital1 (Reg. 39 cnfg_digital_frequencies). T0 APLL frequency/48. T0 APLL frequency/16. T0 APLL frequency/12. T0 APLL frequency/8. T0 APLL frequency/6. T0 APLL frequency/4. T4 APLL frequency/64. T4 APLL frequency/48. T4 APLL frequency/16. T4 APLL frequency/8. T4 APLL frequency/4. - [3:0] Not used. Address (hex): 61 Register Name cnfg_output_frequency (O3) Description (R/W) Register to configure and enable the frequencies available on outputs O3. Bit 3 Bit 2 Default Value 0000 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 output_freq_O3 Bit No. [7:4] Description Not used. Bit Value Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 84 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 61 (cont...) Register Name cnfg_output_frequency (O3) Description FINAL (R/W) Register to configure and enable the frequencies available on outputs O3. Bit 3 Bit 2 Default Value DATASHEET 0000 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 output_freq_O3 Bit No. [3:0] Description output_freq_O3 Configuration of the output frequency available at output O3. Many of the frequencies available are dependent on the frequencies of the T0 APLL and the T4 APLL. These are configured in Reg. 64 and Reg. 65. For more detail see the detailed section on configuring the output frequencies. Bit Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Value Description Output disabled. 2 kHz. 8 kHz. Digital2 (Reg. 39 cnfg_digital_frequencies). Digital1 (Reg. 39 cnfg_digital_frequencies). T0 APLL frequency/48. T0 APLL frequency/16. T0 APLL frequency/12. T0 APLL frequency/8. T0 APLL frequency/6. T0 APLL frequency/4. T4 APLL frequency/64. T4 APLL frequency/48. T4 APLL frequency/16. T4 APLL frequency/8. T4 APLL frequency/4. Revision 5/November 2006 (c) Semtech Corp. Page 85 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 62 Register Name cnfg_output_frequency (O4 & O1) Description FINAL (R/W) Register to configure and enable the frequencies available on outputs O4 and O1. Bit 3 Bit 2 Default Value DATASHEET 1000 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 output_freq_O1 Bit No. [7:4] Description output_freq_O1 Configuration of the output frequency available at output O1. Many of the frequencies available are dependent on the frequencies of the T0 APLL and the T4 APLL. These are configured in Reg. 64 and Reg. 65. For more detail see the detailed section on configuring the output frequencies. Bit Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 output_freq_O4 Value Description Output disabled. 2 kHz. 8 kHz. T0 APLL frequency/2. Digital1 (Reg. 39 cnfg_digital_frequencies). T0 APLL frequency. T0 APLL frequency/16. T0 APLL frequency/12. T0 APLL frequency/8. T0 APLL frequency/6. T0 APLL frequency/4. T4 APLL frequency/64. T4 APLL frequency/48. T4 APLL frequency/16. T4 APLL frequency/8. T4 APLL frequency/4. Output disabled. 2 kHz. 8 kHz. Digital2 (Reg. 39 cnfg_digital_frequencies). Digital1 (Reg. 39 cnfg_digital_frequencies). T0 APLL frequency/48. T0 APLL frequency/16. T0 APLL frequency/12. T0 APLL frequency/8. T0 APLL frequency/6. T0 APLL frequency/4. T4 APLL frequency/2. T4 APLL frequency/48. T4 APLL frequency/16. T4 APLL frequency/8. T4 APLL frequency/4. [3:0] output_freq_O4 Configuration of the output frequency available at output O4. Many of the frequencies available are dependent on the frequencies of the T0 APLL and the T4 APLL. These are configured in Reg. 64 and Reg. 65. For more detail see the detailed section on configuring the output frequencies. Revision 5/November 2006 (c) Semtech Corp. Page 86 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 63 Register Name cnfg_output_frequency (MFrSync) Description FINAL (R/W) Register to configure and enable the frequencies available on MFrSync output. Bit 3 Bit 2 Default Value DATASHEET 1100 0000 Bit 7 MFrSync_en Bit No. 7 Bit 6 FrSync_en Description Bit 5 Bit 4 Bit 1 Bit 0 Bit Value 0 1 0 1 - Value Description Output MFrSync disabled. Output MFrSync enabled. Output FrSync disabled. Output FrSync enabled. - MFrSync_en Register bit to enable the 2 kHz Sync output (MFrSync). FrSync_en Register bit to enable the 8 kHz Sync output (FrSync). Not used. 6 [5:0] Address (hex): 64 Register Name cnfg_T4_DPLL_frequency Description (R/W) Register to configure the T4 Default Value DPLL and several other parameters for the T4 path. Bit 3 Bit 2 Bit 1 T4_DPLL_frequency Bit No. [7:3] [2:0] Description Not used. T4_DPLL_frequency Register to configure the frequency of operation of the DPLL in the T4 path. The frequency of the DPLL will also affect the frequency of the T4 APLL which, in turn, affects the frequencies available at outputs O1 - O4 see Reg. 60 - Reg. 62. It is also possible to not use the T4 DPLL at all, but use the T4 APLL to run directly from the T0 DPLL output, see Reg. 65 (cnfg_TO_DPLL_frequency). If any frequencies are required from the T4 APLL then the T4 DPLL should not be squelched, as the T4 APLL input is squelched and the T4 APLL will free run. Bit Value 000 001 010 011 100 101 110 111 Value Description T4 DPLL squelched (clock off). 77.76 MHz (OC-N rates), T4 APLL frequency = 311.04 MHz. 12E1, T4 APLL frequency = 98.304 MHz. 16E1, T4 APLL frequency = 131.072 MHz. 24DS1, T4 APLL frequency = 148.224 MHz. 16DS1, T4 APLL frequency = 98.816 MHz. E3, T4 APLL frequency = 274.944 MHz. DS3, T4 APLL frequency = 178.944 MHz. 0000 0101 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Revision 5/November 2006 (c) Semtech Corp. Page 87 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 65 Register Name cnfg_T0_DPLL_frequency Description FINAL (R/W) Register to configure the T0 Default Value DPLL and several other parameters for the T0 path. Bit 3 Bit 2 Bit 1 DATASHEET 0000 0001 Bit 7 T4_meas_T0_ ph Bit No. 7 Bit 6 T4_APLL_for_ T0 Description Bit 5 Bit 4 Bit 0 T0_freq_to_T4_APLL T0_DPLL_frequency Bit Value 0 1 Value Description Normal- T4 Path normal operation. T4 DPLL disabled, T4 phase detector used to measure phase between selected T0 input and selected T4 input. T4_meas_T0_ph Register bit to control the feature to use the T4 path to measure phase offset from the T0 path. When enabled the T4 path is disabled and the phase detector is used to measure the phase between the input to the T0 DPLL and the selected T4 input. T4_APLL_for_T0 Register bit to select whether the T4 APLL takes its input from the T4 DPLL or the T0 DPLL. If the T0 DPLL is selected then the frequency is controlled by Bits [5:4], T0_freq_to_T4_APLL. T0_freq_to_T4_APLL Register to select the T0 frequency driven to the T4 APLL when selected by Bit 6, T4_APLL_for_T0. Not used. T0_DPLL_frequency Register to configure the frequency of operation of the DPLL/APLL in the T0 path. This register affects the frequencies available at outputs O1 to O4, see Reg. 60 - Reg. 63. 6 0 1 T4 APLL takes its input from the T4 DPLL. T4 APLL takes its input from the T0 DPLL. [5:4] 00 01 10 11 000 001 010 011 100 101 110 111 12E1, T4 APLL frequency = 98.304 MHz. 16E1, T4 APLL frequency = 131.072 MHz. 24DS1, T4 APLL frequency = 148.224 MHz. 16DS1, T4 APLL frequency = 98.816 MHz. 77.76 MHz, digital feedback, T0 APLL frequency = 311.04 MHz. 77.76 MHz, analog feedback, T0 APLL frequency = 311.04 MHz. 12E1, T0 APLL frequency = 98.304 MHz. 16E1, T0 APLL frequency = 131.072 MHz. 24DS1, T0 APLL frequency = 148.224 MHz. 16DS1, T0 APLL frequency = 98.816 MHz. Not used. Not used. 3 [2:0] Address (hex): 66 Register Name cnfg_T4_DPLL_bw Description (R/W) Register to configure the bandwidth of the T4 DPLL. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 T4_DPLL_bandwidth Bit No. [7:2] Description Not used. Bit Value Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 88 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 66 (cont...) Register Name cnfg_T4_DPLL_bw Description FINAL (R/W) Register to configure the bandwidth of the T4 DPLL. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 T4_DPLL_bandwidth Bit No. [1:0] Description T4_DPLL_bandwidth Register to configure the bandwidth of the T4 DPLL. Bit Value 00 01 10 11 Value Description T4 DPLL 18 Hz bandwidth. T4 DPLL 35 Hz bandwidth. T4 DPLL 70 Hz bandwidth. Not used. Address (hex): 67 Register Name cnfg_T0_DPLL_locked_bw Description (R/W) Register to configure the bandwidth of the T0 DPLL, when phase locked to an input. Bit 3 Bit 2 Default Value 0000 1101 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 T0_DPLL_locked_bandwidth Bit No. [7:4] [3:0] Description Not used. T0_DPLL_locked_bandwidth Register to configure the bandwidth of the T0 DPLL when locked to an input reference. Reg. 3B Bit 7 is used to control whether this bandwidth is used all of the time or automatically switched to when phase locked. Bit Value 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 All other values Value Description T0 DPLL 0.1 Hz locked bandwidth. T0 DPLL 0.3 Hz locked bandwidth. T0 DPLL 0.6 Hz locked bandwidth. T0 DPLL 1.2 Hz locked bandwidth. T0 DPLL 2.5 Hz locked bandwidth. T0 DPLL 4 Hz locked bandwidth. T0 DPLL 8 Hz locked bandwidth. T0 DPLL 18 Hz locked bandwidth. T0 DPLL 35 Hz locked bandwidth. T0 DPLL 70 Hz locked bandwidth. Not used. Revision 5/November 2006 (c) Semtech Corp. Page 89 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 69 Register Name cnfg_T0_DPLL_acq_bw Description FINAL (R/W) Register to configure the bandwidth of the T0 DPLL, when not phase locked to an input. Bit 3 Bit 2 Default Value DATASHEET 0000 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 T0_DPLL_acquisition_bandwidth Bit No. [7:4] [3:0] Description Not used. T0_DPLL_acquisition_bandwidth Register to configure the bandwidth of the T0 DPLL when acquiring phase lock on an input reference. Reg. 3B Bit 7 is used to control whether this bandwidth is not used or automatically switched to when not phase locked. Bit Value 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 All other values Value Description T0 DPLL 0.1 Hz acquisition bandwidth. T0 DPLL 0.3 Hz acquisition bandwidth. T0 DPLL 0.6 Hz acquisition bandwidth. T0 DPLL 1.2 Hz acquisition bandwidth. T0 DPLL 2.5 Hz acquisition bandwidth. T0 DPLL 4 Hz acquisition bandwidth. T0 DPLL 8 Hz acquisition bandwidth. T0 DPLL 18 Hz acquisition bandwidth. T0 DPLL 35 Hz acquisition bandwidth. T0 DPLL 70 Hz acquisition bandwidth. Not used. Address (hex): 6A Register Name cnfg_T4_DPLL_damping Description (R/W) Register to configure the damping factor of the T4 DPLL, along with the gain of Phase Detector 2 in some modes. Bit 3 Bit 2 Default Value 0001 0011 Bit 7 Bit 6 Bit 5 T4_PD2_gain_alog_8k Bit 4 Bit 1 T4_damping Bit 0 Bit No. 7 [6:4] Description Not used. T4_PD2_gain_alog_8k Register to control the gain of the Phase Detector 2 when locking to a reference of 8 kHz or less in analog feedback mode. This setting is only used if automatic gain selection is enabled in Reg. 6C Bit 7, cnfg_T4_DPLL_PD2_gain. Not used. Bit Value - Value Description Gain value of the Phase Detector 2 when locking to an 8 kHz reference in analog feedback mode. 3 - - Revision 5/November 2006 (c) Semtech Corp. Page 90 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 6A (cont...) Register Name cnfg_T4_DPLL_damping Description FINAL (R/W) Register to configure the damping factor of the T4 DPLL, along with the gain of Phase Detector 2 in some modes. Bit 3 Bit 2 Default Value DATASHEET 0001 0011 Bit 7 Bit 6 Bit 5 T4_PD2_gain_alog_8k Bit 4 Bit 1 T4_damping Bit 0 Bit No. [2:0] Description T4_damping Register to configure the damping factor of the T4 DPLL. The bit values corresponds to different damping factors, depending on the bandwidth selected. Damping factor of 5 being the default (011). The Gain Peak for the Damping Factors given in the Value Description (right) are tabulated below. Damping Factor 1.2 2.5 5 10 20 Gain Peak 0.4 dB 0.2 dB 0.1 dB 0.06 dB 0.03 dB Bit Value Value Description T4 DPLL damping factor at the following bandwidths frequency selections: 18 Hz 35 Hz 70 Hz 1.2 1.2 1.2 2.5 2.5 2.5 5 5 5 5 10 10 5 10 20 Not used. Not used. Not used. 001 010 011 100 101 000 110 111 Address (hex): 6B Register Name cnfg_T0_DPLL_damping Description (R/W) Register to configure the damping factor of the T0 DPLL, along with the gain of the Phase Detector 2 in some modes. Bit 3 Bit 2 Default Value 0001 0011 Bit 7 Bit 6 Bit 5 T0_PD2_gain_alog_8k Bit 4 Bit 1 T0_damping Bit 0 Bit No. 7 [6:4] Description Not used. T0_PD2_gain_alog_8k Register to control the gain of the Phase Detector 2 when locking to a reference of 8 kHz or less in analog feedback mode. This setting is only used if automatic gain selection is enabled in Reg. 6D Bit 7, cnfg_T0_DPLL_PD2_gain. Not used. Bit Value - Value Description Gain value of the Phase Detector 2 when locking to an 8 kHz reference in analog feedback mode. 3 - - Revision 5/November 2006 (c) Semtech Corp. Page 91 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 6B (cont...) Register Name cnfg_T0_DPLL_damping Description FINAL (R/W) Register to configure the damping factor of the T0 DPLL, along with the gain of the Phase Detector 2 in some modes. Bit 3 Bit 2 Default Value DATASHEET 0001 0011 Bit 7 Bit 6 Bit 5 T0_PD2_gain_alog_8k Bit 4 Bit 1 T0_damping Bit 0 Bit No. [2:0] Description T0_damping Register to configure the damping factor of the T0 DPLL. The bit values corresponds to different damping factors, depending on the bandwidth selected. Damping factor of 5 being the default (011). The Gain Peak for the Damping Factors given in the Value Description (right) are tabulated below. Damping Factor 1.2 2.5 5 10 20 Gain Peak 0.4 dB 0.2 dB 0.1 dB 0.06 dB 0.03 dB Bit Value Value Description T0 DPLL damping factor at the following bandwidths frequency selections: 8 Hz 18 Hz 35 Hz 70 Hz <4 Hz 5 2.5 1.2 1.2 1.2 5 5 2.5 2.5 2.5 5 5 5 5 5 5 5 5 10 10 5 5 5 10 20 Not used. Not used. Not used. 001 010 011 100 101 000 110 111 Address (hex): 6C Register Name cnfg_T4_DPLL_PD2_gain Description (R/W) Register to configure the Default Value gain of Phase Detector 2 in some modes for the T4 DPLL. Bit 3 Bit 2 Bit 1 T4_PD2_gain_digital 1100 0010 Bit 7 T4_PD2_gain_ enable Bit No. 7 Bit 6 Bit 5 T4_PD2_gain_alog Bit 4 Bit 0 Description T4_PD2_gain_enable Bit Value 0 1 Value Description T4 DPLL Phase Detector 2 not used. T4 DPLL Phase Detector 2 gain enabled and choice of gain determined according to the locking mode: - digital feedback mode - analog feedback mode - analog feedback at 8 kHz. Revision 5/November 2006 (c) Semtech Corp. Page 92 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 6C (cont...) Register Name cnfg_T4_DPLL_PD2_gain Description FINAL (R/W) Register to configure the Default Value gain of Phase Detector 2 in some modes for the T4 DPLL. Bit 3 Bit 2 Bit 1 DATASHEET 1100 0010 Bit 7 T4_PD2_gain_ enable Bit No. [6:4] Bit 6 Bit 5 T4_PD2_gain_alog Bit 4 Bit 0 T4_PD2_gain_digital Description T4_PD2_gain_alog Register to control the gain of Phase Detector 2 when locking to a reference, higher than 8 kHz, in analog feedback mode. This setting is not used if automatic gain selection is disabled in Bit 7, T4_PD2_gain_enable. Not used. T4_PD2_gain_digital Register to control the gain of Phase Detector 2 when locking to a reference in digital feedback mode. This setting is always used if automatic gain selection is disabled in Bit 7, T4_PD2_gain_enable. Bit Value - Value Description Gain value of Phase Detector 2 when locking to a high frequency reference in analog feedback mode. 3 [2:0] - Gain value of Phase Detector 2 when locking to any reference in digital feedback mode. Address (hex): 6D Register Name cnfg_T0_DPLL_PD2_gain Description (R/W) Register to configure the Default Value gain of Phase Detector 2 in some modes for the T0 DPLL. Bit 3 Bit 2 Bit 1 T0_PD2_gain_digital 1100 0010 Bit 7 T0_PD2_gain_ enable Bit No. 7 Bit 6 Bit 5 T0_PD2_gain_alog Bit 4 Bit 0 Description T0_PD2_gain_enable Bit Value 0 1 Value Description T0 DPLL Phase Detector 2 not used. T0 DPLL Phase Detector 2 gain enabled and choice of gain determined according to the locking mode: - digital feedback mode - analog feedback mode - analog feedback at 8 kHz. Gain value of Phase Detector 2 when locking to a high frequency reference in analog feedback mode. [6:4] T0_PD2_gain_alog Register to control the gain of Phase Detector 2 when locking to a reference, higher than 8 kHz, in analog feedback mode. This setting is not used if automatic gain selection is disabled in Bit 7, T0_PD2_gain_enable. Not used. - 3 - - Revision 5/November 2006 (c) Semtech Corp. Page 93 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 6D (cont...) Register Name cnfg_T0_DPLL_PD2_gain Description FINAL (R/W) Register to configure the Default Value gain of Phase Detector 2 in some modes for the T0 DPLL. Bit 3 Bit 2 Bit 1 DATASHEET 1100 0010 Bit 7 T0_PD2_gain_ enable Bit No. [2:0] Bit 6 Bit 5 T0_PD2_gain_alog Bit 4 Bit 0 T0_PD2_gain_digital Description T0_PD2_gain_digital Register to control the gain of Phase Detector 2 when locking to a reference in digital feedback mode. This setting is always used if automatic gain selection is disabled in Bit 7, T0_PD2_gain_enable. Bit Value - Value Description Gain value of Phase Detector 2 when locking to any reference in digital feedback mode. Address (hex): 70 Register Name cnfg_phase_offset [7:0] Bit 6 Bit 5 Description (R/W) Bits [7:0] of the phase offset control register. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 phase_offset_value[7:0] Bit No. [7:0] Description phase_offset_value[7:0] Register forming part of the phase offset control. Bit Value Value Description See Reg. 71, cnfg_phase_offset[15:8] for more details. Revision 5/November 2006 (c) Semtech Corp. Page 94 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 71 Register Name cnfg_phase_offset [15:8] Bit 6 Bit 5 Description FINAL (R/W) Bits [15:8] of the phase offset control register. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 phase_offset_value[15:8] Bit No. [7:0] Description phase_offset_value[15:8] Register forming part of the phase offset control. If the phase offset register is written to when the DPLL is locked to an input, then it is possible that some internal signals become out of synchronization. In order to avoid this, the phase offset is automatically "ramped" to the new value. If the phase offset is only ever adjusted when the device is in Holdover, then this is not necessary, and this automatic "ramping" can be disabled, see Reg. 7C, cnfg_sync_monitor. This register is ignored and has no affect when Phase Build-out is enabled in either Reg. 48 or Reg. 76. Bit Value Value Description The value in this register is to be concatenated with the contents of Reg. 70 cnfg_phase_offset[7:0]. This value is a 16-bit 2's complement signed number. The value multiplied by 6.279 represents the extent of the applied phase offset in picoseconds. The phase offset register is not a control to a "traditional" delay line. This number 6.279 actually represents a fractional portion of the period of an internal 77.76 MHz cycle and can, therefore, be represented more accurately as follows. Each bit value of the register represents the period of the internal 77.76 MHz clock divided by 211. If, for example, the DPLL is locked to a reference that is +1 ppm in frequency with respect to a perfect oscillator, then the period, and hence the phase offset, will be decreased by 1 ppm. Programming a value of 1024 into the phase offset register will produce a complete inversion of the 77.76 MHz output clock. Note...The exact period of the internal 77.76 MHz clock is determined by the current state of the DPLL i.e. in Locked mode its accuracy depends on that of the locked to input, in Holdover or Free-run it depends on the accuracy of the external oscillator. Address (hex): 72 Register Name cnfg_PBO_phase_offset Description (R/W) Register to offset the mean Default Value time error of Phase Build-out events. Bit 3 Bit 2 Bit 1 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 PBO_phase_offset Bit No. [7:6] Description Not used. Bit Value Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 95 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 72 (cont...) Register Name cnfg_PBO_phase_offset Description FINAL (R/W) Register to offset the mean Default Value time error of Phase Build-out events. Bit 3 Bit 2 Bit 1 DATASHEET 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 PBO_phase_offset Bit No. [5:0] Description PBO_phase_offset Each time a Phase Build-out event is triggered, there is an uncertainty of up to 5 ns introduced which translates to a phase hit on the output. The mean error over a large number of events is designed to be zero. This register can be used to introduce a fixed offset into each PBO event. This will have the effect of moving the mean error positive or negative in time. Bit Value Value Description The value in this register is a 6-bit 2's complement number. The value multiplied by 0.101 gives the programmed offset in nanoseconds. Values greater than +1.4 ns or less than -1.4 ns should NOT be used as they may cause internal mathematical errors. Address (hex): 73 Register Name cnfg_phase_loss_fine_limit Description (R/W) Register to configure some Default Value of the parameters of the T0 DPLL phase detector. Bit 3 Bit 2 Bit 1 phase_loss_fine_limit Bit Value 0 1 Value Description Phase loss indication only triggered by other means. Phase loss triggered when phase error exceeds the limit programmed in phase_loss_fine_limit, Bits [2:0]. 1010 0010 Bit 7 fine_limit_en Bit No. 7 Bit 6 noact_ph_loss Description Bit 5 narrow_en Bit 4 Bit 0 fine_limit_en Register bit to enable the phase_loss_fine_limit Bits [2:0]. When disabled, phase lock/loss is determined by the other means within the device. This must be disabled when multi-UI jitter tolerance is required, see Reg. 74, cnfg_phase_loss_course_limit. noact_ph_loss The DPLL detects that an input has failed very rapidly. Normally, when the DPLL detects this condition, it does not consider phase lock to be lost and will phase lock to the nearest edge (180) when a source becomes available again, hence giving tolerance to missing cycles. If phase loss is indicated, then frequency and phase locking is instigated (360 locking). This bit can be used to force the DPLL to indicate phase loss immediately when no activity is detected. 6 0 1 No activity on reference does not trigger phase lost indication. No activity triggers phase lost indication. Revision 5/November 2006 (c) Semtech Corp. Page 96 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 73 (cont...) Register Name cnfg_phase_loss_fine_limit Description FINAL (R/W) Register to configure some Default Value of the parameters of the T0 DPLL phase detector. Bit 3 Bit 2 Bit 1 DATASHEET 1010 0010 Bit 7 fine_limit_en Bit No. 5 [4:3] [2:0] Bit 6 noact_ph_loss Description Bit 5 narrow_en Bit 4 Bit 0 phase_loss_fine_limit Bit Value 0 1 000 001 010 011 100 101 110 111 Value Description narrow_en (test control bit) Set to 1 (default value) Not used. phase_loss_fine_limit When enabled by Bit 7, this register coarsely sets the phase limit at which the device indicates phase lost or locked. The default value of 2 (010) gives a window size of around 90 - 180. The phase position of the inputs to the DPLL has to be within the window limit for 1 - 2 seconds before the device indicates phase lock. If it is outside the window for any time then phase loss is immediately indicated. For most cases the default value of 2 (010) is satisfactory. The window size changes in proportion to the value, so a value of 1 (001) will give a narrow phase acceptance or lock window of approximately 45 - 90. Set to 1 Do not use. Indicates phase loss continuously. Small phase window for phase lock indication. Recommended value. ) ) ) Larger phase window for phase lock indication. ) ) Address (hex): 74 Register Name cnfg_phase_loss_coarse_limit Description (R/W) Register to configure some Default Value of the parameters of the T0 DPLL phase detector. Bit 3 Bit 2 Bit 1 1000 0101 Bit 7 coarse_lim_ phaseloss_en Bit No. 7 Bit 6 wide_range_en Bit 5 multi_ph_resp Bit 4 Bit 0 phase_loss_coarse_limit Description coarse_lim_phaseloss_en Register bit to enable the coarse phase detector, whose range is determined by phase_loss_coarse_limit Bits [3:0]. This register sets the limit in the number of input clock cycles (UI) that the input phase can move by before the DPLL indicates phase lost. Bit Value 0 1 Value Description Phase loss not triggered by the coarse phase lock detector. Phase loss triggered when phase error exceeds the limit programmed in phase_loss_coarse_limit, Bits [3:0]. Revision 5/November 2006 (c) Semtech Corp. Page 97 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 74 (cont...) Register Name cnfg_phase_loss_coarse_limit Description FINAL (R/W) Register to configure some Default Value of the parameters of the T0 DPLL phase detector. Bit 3 Bit 2 Bit 1 DATASHEET 1000 0101 Bit 7 coarse_lim_ phaseloss_en Bit No. 6 Bit 6 wide_range_en Bit 5 multi_ph_resp Bit 4 Bit 0 phase_loss_coarse_limit Description wide_range_en To enable the device to be tolerant to large amounts of applied jitter and still do direct phase locking at the input frequency rate (up to 77.76 MHz), a wide range phase detector and phase lock detector is employed. This bit enables the wide range phase detector. This allows the device to be tolerant to, and therefore keep track of, drifts in input phase of many cycles (UI). The range of the phase detector is set by the same register used for the phase loss coarse limit (Bits [3:0]). multi_ph_resp Enables the phase result from the coarse phase detector to be used in the DPLL algorithm. Bit 6 should also be set when this is activated. The coarse phase detector can measure and keep track over many thousands of input cycles, thus allowing excellent jitter and wander tolerance. This bit enables that phase result to be used in the DPLL algorithm, so that a large phase measurement gives a faster pull-in of the DPLL. If this bit is not set then the phase measurement is limited to 360 which can give a slower pull-in rate at higher input frequencies, but could also be used to give less overshoot. Setting this bit in direct locking mode, for example with a 19.44 MHz input, would give the same dynamic response as a 19.44 MHz input used with 8 k locking mode, where the input is divided down internally to 8 kHz first. Not used. Bit Value 0 1 Value Description Wide range phase detector off. Wide range phase detector on. 5 0 DPLL phase detector limited to 360 (1 UI). However it will still remember its original phase position over many thousands of UI if Bit 6 is set. DPLL phase detector also uses the full coarse phase detector result. It can now measure up to: 360 x 8191 UI = 2,948,760. 1 4 - - Revision 5/November 2006 (c) Semtech Corp. Page 98 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 74 (cont...) Register Name cnfg_phase_loss_coarse_limit Description FINAL (R/W) Register to configure some Default Value of the parameters of the T0 DPLL phase detector. Bit 3 Bit 2 Bit 1 DATASHEET 1000 0101 Bit 7 coarse_lim_ phaseloss_en Bit No. [3:0] Bit 6 wide_range_en Bit 5 multi_ph_resp Bit 4 Bit 0 phase_loss_coarse_limit Description phase_loss_coarse_limit Sets the range of the coarse phase loss detector and the coarse phase detector. When locking to a high frequency signal, and jitter tolerance greater than 0.5 UI is required, then the DPLL can be configured to track phase errors over many input clock periods. This is particularly useful with very low bandwidths. This register configures how many UI over which the input phase can be tracked. It also sets the range of the coarse phase loss detector, which can be used with or without the multi-UI phase capture range capability. This register value is used by Bits 6 and 7. Bit Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100-1111 Value Description Input phase error tracked over 1 UI. Input phase error tracked over 3 UI. Input phase error tracked over 7 UI. Input phase error tracked over 15 UI. Input phase error tracked over 31 UI. Input phase error tracked over 63 UI. Input phase error tracked over 127 UI. Input phase error tracked over 255 UI. Input phase error tracked over 511 UI. Input phase error tracked over 1023 UI. Input phase error tracked over 2047 UI. Input phase error tracked over 4095 UI. Input phase error tracked over 8191 UI. Address (hex): 76 Register Name cnfg_phasemon Description (R/W) Register to configure the noise rejection function for low frequency inputs. Bit 3 Bit 2 Default Value 0000 0110 Bit 7 ip_noise_ window Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Description ip_noise_window Register bit to enable a window of 5% tolerance around low-frequency inputs (2, 4 and 8 kHz). This feature ensures that any edge caused by noise outside the 5% window where the edge is expected will not be considered within the DPLL. This reduces any possible phase hit when a low-frequency connection is removed and contact bounce is possible. Not used. Bit Value 0 1 Value Description DPLL considers all edges for phase locking. DPLL ignores input edges outside a 95% to 105% window. [6:0] - - Revision 5/November 2006 (c) Semtech Corp. Page 99 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 77 Register Name sts_current_phase [7:0] Bit 6 Bit 5 Description FINAL (RO) Bits [7:0] of the current phase register. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 current_phase[7:0] Bit No. [7:0] Description current_phase Bits [7:0] of the current phase register. See Reg. 78 sts_current_phase [15:8] for details. Bit Value Value Description See Reg. 78 sts_current_phase [15:8] for details. Address (hex): 78 Register Name sts_current_phase [15:8] Bit 6 Bit 5 Description (RO) Bits [15:8] of the current phase register. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 Bit 4 Bit 1 Bit 0 current_phase[15:8] Bit No. [7:0] Description current_phase Bits [15:8] of the current phase register. This register is used to read either from the phase detector of either the T0 DPLL or the T4 DPLL, according to Reg. 4B Bit 4 T4_T0_select. The value is averaged in the phase averager (filter with approx. 100 Hz bandwidth) before being made available. Bit Value Value Description The value in this register should be concatenated with the value in Reg. 77 sts_current_phase [7:0]. This 16-bit value is a 2's complement signed integer. The value multiplied by 0.707 is the averaged value of the current phase error, in degrees, as measured at the DPLL's phase detector. Address (hex): 79 Register Name cnfg_phase_alarm_timeout Description (RO) Register to configure how long before a phase alarm is raised on an input Bit 3 Bit 2 Default Value 0011 0010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 timeout_value Bit No. [7:6] Description Not used. Bit Value Value Description - Revision 5/November 2006 (c) Semtech Corp. Page 100 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 79 (cont...) Register Name cnfg_phase_alarm_timeout Description FINAL (RO) Register to configure how long before a phase alarm is raised on an input Bit 3 Bit 2 Default Value DATASHEET 0011 0010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 timeout_value Bit No. [5:0] Description timeout_value Phase alarms can only be raised on an input when the T0 DPLL is attempting to lock to it. Once an input has been rejected due to a phase alarm, there is no way to measure whether it is good again, because it is no longer selected by the DPLL. The phase alarms can either remain until reset by software, or timeout after 128 second, as selected in Reg. 34 Bit 6, phalarm_timeout Bit Value Value Description This 6-bit unsigned integer represents the length of time before a phase alarm will be raised on an input. The value multiplied by 2 gives the time in seconds. This time value is the time that the controlling state machine will spend in Pre-locked, Pre-locked2 or Phase-lost modes before setting the phase alarm on the selected input. Address (hex): 7A Register Name cnfg_sync_pulses Description (R/W) Register to configure the Sync outputs, and select the source for the 2 kHz and 8 kHz outputs from O1 to O4. Bit 3 8k_invert Description 2k_8k_from_T4 Register to select the source (T0 or T4) for the 2 kHz and 8 kHz outputs available from O1 to O4. Not used. 8k_invert Register bit to invert the 8 kHz output from FrSync. 8k_pulse Register bit to enable the 8 kHz output from FrSync to be either pulsed or 50:50 duty cycle. Output 03 must be enabled to use "pulsed output" mode on the FrSync output, and then the pulse width on the FrSync output will be equal to the period of the output programmed on O3. 2k_invert Register bit to invert the 2 kHz output from MFrSync. Bit Value 0 1 0 1 0 1 Bit 2 8k_pulse Default Value 0000 0000 Bit 7 2k_8k_from_T4 Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 1 2k_invert Bit 0 2k_pulse Value Description 2/8 kHz on O1 to O4 generated from the T0 DPLL. 2/8 kHz on O1 to O4 generated from the T4 DPLL. 8 kHz FrSync output not inverted. 8 kHz FrSync output inverted. 8 kHz FrSync output not pulsed. 8 kHz FrSync output pulsed. [6:4] 3 2 1 0 1 2 kHz MFrSync output not inverted. 2 kHz MFrSync output inverted. Revision 5/November 2006 (c) Semtech Corp. Page 101 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 7A (cont...) Register Name cnfg_sync_pulses Description FINAL (R/W) Register to configure the Sync outputs, and select the source for the 2 kHz and 8 kHz outputs from O1 to O4. Bit 3 8k_invert Bit 2 8k_pulse Default Value DATASHEET 0000 0000 Bit 7 2k_8k_from_T4 Bit No. 0 Bit 6 Bit 5 Bit 4 Bit 1 2k_invert Bit 0 2k_pulse Description 2k_pulse Register bit to enable the 2 kHz output from MFrSync to be either pulsed or 50:50 duty cycle. Output 03 must be enabled to use "pulsed output" mode on the MFrSync output, and then the pulse width on the MFrSync output will be equal to the period of the output programmed on O3. Bit Value 0 1 Value Description 2 kHz MFrSync output not pulsed. 2 kHz MFrSync output pulsed. Address (hex): 7B Register Name cnfg_sync_phase Description (R/W) Register to configure the behavior of the synchronization for the external frame reference. Bit 3 Bit 2 Default Value 0000 0000 Bit 7 indep_FrSync/ MFrSync Bit No. 7 Bit 6 Sync_OC-N_ rates Description Bit 5 Bit 4 Bit 1 Sync_phase Bit 0 Bit Value 0 1 Value Description MFrSync & FrSync outputs are always aligned with other output clocks. MFrSync & FrSync outputs are independent of other output clocks. indep_FrSync/MFrSync This allows the option of either maintaining alignment of FrSync and other clock outputs during synchronization from the SYNC2K input, or whether to not maintain alignment to all clocks and so not disturb any of the output clocks Sync_OC-N_rates This allows the SYNC2K input to synchronize the OC-3 derived clocks in order to maintain alignment between the FrSync output and output clocks and allow a finer sampling precision of the SYNC2K input of either 19.44 MHz or 38.88 MHz. 6 0 1 The OC-N rate clocks are not affected by the SYNC2K input. The SYNC2K input is sampled with a 6.48 MHz precision. 6.48MHz should be provided as the input reference clock. Allows the SYNC2K to operate with a 19.44 MHz or 38.88 MHz input clock reference. Input sampling and output alignment to 19.44 MHz is used when the current clock input is 19.44 MHz, otherwise 38.88 MHz sampling precision is used. [5:2] Not used. Revision 5/November 2006 (c) Semtech Corp. Page 102 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 7B (cont...) Register Name cnfg_sync_phase Description FINAL (R/W) Register to configure the behavior of the synchronization for the external frame reference. Bit 3 Bit 2 Default Value DATASHEET 0000 0000 Bit 7 indep_FrSync/ MFrSync Bit No. [1:0] Bit 6 Sync_OC-N_ rates Description Bit 5 Bit 4 Bit 1 Sync_phase Bit 0 Bit Value 00 01 10 11 Value Description On target. 0.5 U.I. early 1 U.I. late 0.5 U.I. late. Sync_phase Register to control the sampling of the external Sync input. Nominally the falling edge of the input is aligned with the falling edge of the reference clock. The margin is 0.5 U.I. (Unit Interval). Address (hex): 7C Register Name cnfg_sync_monitor Description (R/W) Register to control the phase offset automatic ramping feature. Bit 3 Bit 2 Default Value 0010 1011 Bit 7 ph_offset_ramp Bit No. 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Description ph_offset_ramp Register bit to force an internal phase offset calibration, see Reg. 71, Cnfg_Phase_Offset. The calibration routine is transparent to the User and puts the device in holdover while it internally ramps the phase offset to zero, resets all internal output and feedback dividers and then ramps the phase offset to the current programmed value from Reg. 70 or 71., holdover is then turned off. Throughout this procedure, no change in output phase offset is visible. Not used. Bit Value 0 Value Description Phase offset automatically ramped from the old value to the new value when there is a change in Reg. 70 or 71. Start phase offset internal calibration routine. This bit is reset to 0 when this is complete. 1 [6:0] - - Revision 5/November 2006 (c) Semtech Corp. Page 103 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Address (hex): 7D Register Name cnfg_interrupt Description FINAL (R/W) Register to configure interrupt output. Bit 3 Bit 2 GPO_en Default Value DATASHEET 0000 0010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 tristate_en Bit 0 int_polarity Bit No. [7:3] 2 Description Not used. GPO_en (Interrupt General Purpose Output). If the interrupt output pin is not required, then setting this bit will allow the pin to be used as a general purpose output. The pin will be driven to the state of the polarity control bit, int_polarity. tristate_en The interrupt can be configured to be either connected directly to a processor, or wired together with other sources. int_polarity The interrupt pin can be configured to be active High or Low. Bit Value 0 1 Value Description Interrupt output pin used for interrupts. Interrupt output pin used for GPO purpose. 1 0 1 Interrupt pin always driven when inactive. Interrupt pin only driven when active, highimpedance when inactive. Active Low - pin driven Low to indicate active interrupt. Active High - pin driven High to indicate active interrupt. 0 0 1 Address (hex): 7E Register Name cnfg_protection Description (R/W) Protection register to protect against erroneous software writes. Bit 3 Bit 2 Default Value 1000 0101 Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 protection_value Bit No. [7:0] Description protection_value This register can be used to ensure that the software writes a specific value to this register, before being able to modify any other register in the device. Three modes of protection are offered, (i) protected (ii) fully unprotected (iii) single unprotected. When protected, no other register in the device can be written to. When fully unprotected, any writeable register in the device can be written to. When single unprotected, only one register can be written before the device automatically re-protects itself. Bit Value 0000 0000 - 1000 0100 1000 0101 1000 0110 1000 0111 - 1111 1111 Value Description Protected mode. Fully unprotected. Single unprotected. Protected mode. Revision 5/November 2006 (c) Semtech Corp. Page 104 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Electrical Specifications JTAG The JTAG connections on the ACS8522 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1[5], with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support INTEST. However this does not affect board testing. 2. In common with some other manufacturers, pin TRST is internally pulled Low to disable JTAG by default. The standard is to pull High. The polarity of TRST is as the standard: TRST High to enable JTAG boundary scan mode, TRST Low for normal operation. The JTAG timing diagram is shown in Figure 14. FINAL Over-voltage Protection DATASHEET The ACS8522 may require Over-Voltage Protection on input reference clock ports according to ITU recommendation K.41[16]. Semtech protection devices are recommended for this purpose (see separate Semtech data book). ESD Protection Suitable precautions should be taken to protect against electrostatic damage during handling and assembly. This device incorporates ESD protection structures that protect the device against ESD damage at ESD input levels up to at least +/2kV using the Human Body Model (HBD) MIL-STD-883D Method 3015.7, for all pins. Latchup Protection This device is protected against latchup for input current pulses of magnitude up to at least 100 mA to JEDEC Standard No. 78 August 1997. Figure 14 JTAG Timing tCYC TCK tSUR TMS TDI tDOD TDO F8110D_022JTAGTiming_01 tHT Table 21 JTAG Timing (for use with Figure 14) Parameter Cycle Time TMS/TDI to TCK rising edge time TCK rising to TMS/TDI hold time TCK falling to TDO valid Symbol tCYC tSUR tHT tDOD Minimum 50 3 23 Typical Maximum 5 Units ns ns ns ns Revision 5/November 2006 (c) Semtech Corp. Page 105 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Maximum Ratings FINAL DATASHEET Important Note: The Absolute Maximum Ratings, Table 22, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 22 Absolute Maximum Ratings Parameter Supply Voltage VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7, VD1+, VD2+,VD3+, VA1+, VA2+, VA3+, VDD_DIFF Input Voltage (non-supply pins) Output Voltage (non-supply pins) Ambient Operating Temperature Range Storage Temperature Symbol VDD Minimum -0.5 Maximum 3.6 Units V VIN VOUT TA TSTOR -40 -50 5.5 5.5 +85 +150 V V oC oC Operating Conditions Table 23 Operating Conditions Parameter Power Supply (dc voltage) VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7, VD1+, VD2+,VD3+, VA1+, VA2+, VA3+, VDD_DIFF Power Supply (dc voltage) VDD5V Ambient Temperature Range Supply Current (Typical - one 19 MHz output) Total Power Dissipation Symbol VDD Minimum 3.0 Typical 3.3 Maximum 3.6 Units V VDD5V TA IDD PTOT 3.0 -40 - 3.3/5.0 110 360 5.5 +85 200 720 V oC mA mW DC Characteristics Table 24 DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated Parameter VIN High VIN Low Input Current Symbol VIH VIL IIN Minimum 2 Typical Maximum 0.8 10 Units V V A Revision 5/November 2006 (c) Semtech Corp. Page 106 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Across all operating conditions, unless otherwise stated Parameter VIN High VIN Low Pull-up Resistor Input Current Symbol VIH VIL PU IIN Minimum 2 25 Typical Maximum 0.8 95 120 Units V V k FINAL DATASHEET Table 25 DC Characteristics: TTL Input Port with Internal Pull-up Table 26 DC Characteristics: TTL Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated Parameter VIN High VIN Low Pull-down Resistor (except TCK input) Pull-down Resistor (TCK input only) Input Current Symbol VIH VIL PD PD IIN Minimum 2 25 12.5 Typical Maximum 0.8 95 47.5 120 Units V V k k A Table 27 DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated Parameter VOUT Low (lOL = 4 mA) VOUT High (lOL = 4 mA) Drive Current Symbol VOL VOH ID Minimum 0 2.4 Typical Maximum 0.4 4 Units V V mA Table 28 DC Characteristics: PECL Output Port Across all operating conditions, unless otherwise stated Parameter PECL Output Low Voltage (Note (i)) PECL Output High Voltage (Note (i)) PECL Output Differential Voltage (Note (i)) Note: Symbol VOLPECL VOHPECL VODPECL Minimum VDD-2.10 VDD-1.25 580 Typical Maximum VDD-1.62 VDD-0.88 900 Units V V mV (i) With 50 load on each pin to VDD-2 V, i.e. 82 to GND and 130 to VDD. Revision 5/November 2006 (c) Semtech Corp. Page 107 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS FINAL V DD 130 DATASHEET Figure 15 Recommended Line Termination for PECL Output Ports Z0 = 50 O1POS 82 Fully 130 Programmable Output Frequencies Z0 = 50 O1NEG 82 GND VDD = +3.3 V Z0 = Transmission Line Impedance F8522D_024PECL_02 Table 29 DC Characteristics: LVDS Output Port Across all operating conditions, unless otherwise stated Parameter LVDS Output High Voltage (Note (i)) LVDS Output Low Voltage (Note (i)) LVDS Differential Output Voltage LVDS Change in Magnitude of Differential Output Voltage for complementary States (Note (i)) LVDS Output Offset Voltage Temperature = 25oC (Note (i)) Symbol VOHLVDS VOLLVDS VODLVDS VDOSLVDS Minimum 0.885 250 Typical Maximum 1.585 450 25 Units V V mV mV VOSLVDS 1.125 - 1.275 V Note: (i) With 100 load between the differential outputs. Figure 16 Recommended Line Termination for LVDS Output Port O1POS Z0 = 50 100 Fully Programmable Output Frequencies O1NEG Z0 = 50 Z0 = Transmission Line Impedance F8522D_025LVDS_02 Revision 5/November 2006 (c) Semtech Corp. Page 108 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Jitter Performance FINAL DATASHEET Output jitter generation measured over 60 second interval, UI pk-pk max measured using C-MAC E2747 12.800 MHz TCXO on ICT Flexacom tester. Table 30 Output Jitter Generation Test Definition Specification G813[11] for 155 MHz o/p option 1 Filter 65 kHz - 1.3 MHz Bandwidth 4 Hz Conditions I/P Freq 19 MHz Lock Mode Direct lock 8k lock G813[11] & G812[10] for 2.048 MHz option 1 G813[11] for 155 MHz o/p option 2 20 Hz - 100 kHz 12 kHz - 1.3 MHz 12 kHz - 1.3 MHz 12 kHz - 1.3 MHz 12 kHz - 1.3 MHz 12 kHz - 1.3 MHz 12 kHz - 1.3 MHz G812[10] for 1.544 MHz o/p G812[10] for 155 MHz electrical G812[10] for 155 MHz electrical ETS-300-462-3 [3] Jitter Spec UI 0.1 pk-pk ACS8522 Jitter UI (TYP) 0.067 pk-pk 0.065 pk-pk 4 Hz 18 Hz 8 Hz 4 Hz 2.5 Hz 1.2 Hz 0.6 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 2.048 MHz 8k lock 19 MHz 19 MHz 19 MHz 19 MHz 19 MHz 19 MHz 0.05 pk-pk 0.012 pk-pk 0.072 pk-pk 0.072 pk-pk 0.078 pk-pk 0.078 pk-pk 0.078 pk-pk 0.076 pk-pk 0.006 pk-pk 0.118 pk-pk 0.065 pk-pk 0.012 pk-pk 0.012 pk-pk 0.012 pk-pk 0.118 pk-pk 0.067 pk-pk 0.027 pk-pk 0.017 pk-pk 0.118 pk-pk 0.067 pk-pk 0.076 pk-pk 0.006 rms 0.018 pk-pk 0.003 rms Direct lock/ 0.1 pk-pk 8k lock Direct lock/ 0.1 pk-pk 8k lock Direct lock/ 0.1 pk-pk 8k lock Direct lock/ 0.1 pk-pk 8k lock Direct lock/ 0.1 pk-pk 8k lock Direct lock/ 0.1 pk-pk 8k lock 0.05 pk-pk 0.5 pk-pk 0.075 pk-pk 0.5 pk-pk 0.2 pk-pk 0.05 pk-pk 0.5 pk-pk 0.1 pk-pk 1.5 pk-pk 0.15 pk-pk 1.5 pk-pk 0.15 pk-pk 0.1 pk-pk 0.01 rms 10 Hz - 40 kHz 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 20 Hz - 100 kHz 49 Hz - 100 kHz 20 Hz - 100 kHz 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 100 Hz - 0.4 MHz 1.544 MHz 8k lock 19 MHz 19 MHz 8k lock 8k lock for 2.048 MHz SEC o/p 2.048 MHz 8k lock 2.048 MHz 8k lock 2.048 MHz 8k lock 19 MHz 19 MHz 19 MHz 19 MHz 19 MHz 19 MHz 19 MHz 8k lock 8k lock 8k lock 8k lock 8k lock 8k lock 8k lock ETS-300-462-3[3] for 2.048 MHz SEC o/p ETS-300-462-3[3] for 2.048 MHz SSU o/p ETS-300-462-5[4] for 155 MHz o/p ETS-300-462-5[4] for 155 MHz o/p GR-253-CORE[17] net i/f, 51.84 MHz o/p GR-253-CORE[17] net i/f, 51.84 MHz o/p GR-253-CORE[17] net i/f, 155 MHz o/p GR-253-CORE[17] net i/f, 155 MHz o/p GR-253-CORE[17]cat II elect i/f, 155 MHz 20 kHz to 0.4 MHz 4 Hz 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 12 kHz - 1.3 MHz 4 Hz 4 Hz 4 Hz GR-253-CORE[17] cat II elect i/f, 51.84 MHz 12 kHz - 400 kHz 4 Hz 19 MHz 8k lock 0.1 pk-pk 0.01 rms Revision 5/November 2006 (c) Semtech Corp. Page 109 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Table 30 Output Jitter Generation Test Definition Specification GR-253-CORE[17] DS1 i/f, 1.544 MHz Filter 10 Hz - 40 kHz Bandwidth 4 Hz Conditions I/P Freq Lock Mode Jitter Spec UI 0.1 pk-pk 0.01 rms AT&T 62411[2] for 1.544 MHz AT&T 62411[2] for 1.544 MHz AT&T 62411 [2] FINAL DATASHEET ACS8522 Jitter UI (TYP) 0.001 pk-pk <0.001 rms <0.001 rms <0.001 rms <0.001 rms <0.001 rms 0.012 rms 0.012 pk-pk 0.012 pk-pk 0.006 pk-pk 0.006 pk-pk 0.006 pk-pk 1.544 MHz 8k lock 10 Hz - 8 kHz 8 Hz - 40 kHz 10 Hz - 40 kHz Broadband DC - 100 kHz 18 kHz - 100 kHz 20 Hz - 100 kHz 10 Hz - 40kHz 8 kHz - 40kHz > 10 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 4 Hz 1.544 MHz 8k lock 1.544 MHz 8k lock 1.544 MHz 8k lock 1.544 MHz 8k lock 2.048 MHz 8k lock 2.048 MHz 8k lock 2.048 MHz 8k lock 1.544 MHz 8k lock 1.544 MHz 8k lock 1.544 MHz 8k lock 0.02 rms 0.025 rms 0.025 rms 0.05 rms 0.25 rms 0.05 pk-pk 0.05 pk-pk 5.0 pk-pk 0.1 pk-pk 0.05 pk-pk for 1.544 MHz AT&T 62411[2] for 1.544 MHz G-742[8] for 2.048 MHz G-742[8] for 2.048MHz G-736 [7] for 2.048MHz GR-499-CORE[18] & G824[14] for 1.544 MHz GR-499-CORE[18] & G824[14] for 1.544 MHz GR-1244-CORE[19] for 1.544 MHz Note...This table is only for comparing the ACS8522 output jitter performance against values and quoted in various specifications for given conditions. It should not be used to infer compliance to any other aspects of these specifications. Revision 5/November 2006 (c) Semtech Corp. Page 110 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Input/Output Timing Input/Output 8 kHz input +8.2 1.5 ns 8 kHz output FrSync (8 kHz) 6.48 MHz input +4.7 1.5 ns 6.48 MHz output 8 kHz -0.4 0.5 ns -1.2 0.5 ns FINAL DATASHEET Figure 17 Input/Output Timing with Phase Build-out Off Delay Output MFrSync (2 kHz) Min/Max Phase Alignment (FrSync Alignment switched on) 19.44 MHz input +4.3 1.5 ns 19.44 MHz output 2 kHz -0.0 0.5 ns DS1 (1.544 MHz) 25.92 MHz input +4.7 1.5 ns 25.92 MHz output E1 (2.048 MHz) -1.2 1.25 ns -1.2 1.25 ns 38.88 MHz input +4.6 1.5 ns 38.88 MHz output DS3 (44.736 MHz) -3.75 1.25 ns E3 (34.368 MHz) 51.84 MHz input +3.0 1.5 ns 51.84 MHz output 6.48 MHz -3.75 1.25 ns -3.75 1.25 ns 77.76 MHz input +5.3 1.5 ns 77.76 MHz output 19.44 MHz -3.75 1.25 ns 25.92 MHz -3.75 1.25 ns 38.88 MHz -3.75 1.25 ns 51.84 MHz -3.75 1.25 ns 77.76 MHz -3.75 1.25 ns 155.52 MHz -3.75 1.25 ns 311.04 MHz -3.75 1.25 ns F8523D_021IP_OPTiming_02 Revision 5/November 2006 (c) Semtech Corp. Page 111 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Package Information Figure 18 LQFP Package D 2 3 FINAL DATASHEET D1 1 AN2 AN3 1 R1 S E 2 E1 1 3 4 L1 A A AN1 B R2 B Section A-A AN4 L 123 5 b e 7 Section B-B A A2 c 7 c1 7 Seating plane A1 6 b b1 7 8 Notes 1 2 3 The top package body may be smaller than the bottom package body by as much as 0.15 mm. To be determined at seating plane. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Details of pin 1 identifier are optional but will be located within the zone indicated. Exact shape of corners can vary. A1 is defined as the distance from the seating plane to the lowest point of the package body. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. Shows plating. 4 5 6 7 8 Table 31 64 Pin LQFP Package Dimension Data (for use with Figure 18) Dimensions in mm Min. Nom. Max. D/E D1/E1 A A1 A2 e AN1 AN2 AN3 AN4 11o 11o 12o 13o 0o 0o 3.5o 7o R1 R2 L L1 S b b1 c c1 1.40 0.05 1.35 0.08 0.08 0.45 - 0.20 0.17 0.17 0.09 0.09 0.22 0.20 - 12.00 10.00 1.50 0.10 1.40 0.50 12o 1.60 0.15 1.45 13o 0.60 1.00 (ref) - 0.20 0.75 0.27 0.23 0.20 0.16 Revision 5/November 2006 (c) Semtech Corp. Page 112 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Thermal Conditions FINAL DATASHEET The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 19 Typical 64 Pin LQFP Footprint 1.85 mm 13.0 13 mm ( (1) Pitch 0.5 m ch mm Width 0.3 m idth .3 mm F8525D_029LQFootprt64 Notes: (i) Solderable to this limit. (ii) Square package - dimensions apply in both X and Y directions. (iii) Typical example. The user is responsible for ensuring compatibility with PCB manufacturing process, etc. Revision 5/November 2006 (c) Semtech Corp. Page 113 14.3 mm 14 10.6 10 mm www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Application Information Figure 20 Simplified Application Schematic FINAL DATASHEET VDD3 VDD5v VDD P1 5v 0v term_connect (+) C2 100uF C3 100nF VDD2 IC2 VOUT 3 VIN 1 GND 2 +) VDDA C4 C5 100nF AGND Optional Processor Interface connections CSB INTREQSDO SDI SrcSwit SCLK ( EZ1086CM-3.3 10uF_TANT ZD1 BZV90C-5.6v DGND2 DGND DGND3 O4 O3 VDD O2 VDDA C15 100nF AGND Typical 12.8MHz oscillator C-MAC E2747_12.8MHz AGND C6 100nF R1 10R VDDA VDD3 C7 100nF DGND3 R2 10R AGND C8 100nF DGND C14 100nF DGND 49 TCK 50 TDO 51 TDI 52 SDO 53 DGND6 54 VDD7 55 O2 56 O3 57 VA3+ 58 AGND4 59 O4 60 IC8 61 IC9 62 IC10 63 IC11 64 SONSDHB VDD 9 VS C17 100nF DGND NC NC 3 NC 10 GNDb 1 OP 5 GND 4 DGND X1 17 FrSync 18 MFrSync 19 O1POS 20 O1NEG 21 GND_DIFF 22 VDD_DIFF 23 IC3 24 IC4 25 IC5 26 IC6 27 VDD5V 28 SYNC2K 29 SEC1 30 SEC2 31 DGND4 32 VDD1 1 AGND1 2 IC1 3 AGND2 4 VA1+ 5 INTREQ 6 REFCLK 7 DGND1 8 VD1+ 9 VD2+ 10 DGND2 11 DGND3 12 VD3+ 13 SRCSW 14 VA2+ 15 AGND3 16 IC2 IC1 ACS8522 PORB 48 SCLK 47 VDD6 46 VDD5 45 CSB 44 SDI 43 CLKE 42 TMS 41 DGND5 40 VDD4 39 VDD3 38 TRST 37 VDD2 36 IC7 35 SEC4 34 SEC3 33 PORB C13 1nF DGND VDD 2 Revision 5/November 2006 (c) Semtech Corp. 8 NC 7 NC 6 NC DGND C12 100nF VDD VDD2 optional only needed for 5v protection VDD5v C9 100nF VDD DGND2 C11 100nF DGND C10 100nF DGND FrSync MFrSync O1P O1N DGND2 SYNC2K SEC1 SEC2 SEC3 SEC4 DGND F8522D_032SimpleSchem_01 Page 114 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Abbreviations APLL BITS DFS DPLL DS1 DTO E1 I/O LOS LQFP LVDS MTIE NE OCXO PBO PDH PECL PFD PLL POR ppb ppm pk-pk rms RO R/W SDH SEC SETS SONET SSU STM TDEV TCXO UI XO FINAL References [1] ANSI T1.101-1999 (1999) Synchronization Interface Standard DATASHEET Analogue Phase Locked Loop Building Integrated Timing Supply Digital Frequency Synthesis Digital Phase Locked Loop 1544 kbit/s interface rate Discrete Time Oscillator 2048 kbit/s interface rate Input - Output Loss Of Signal Low profile Quad Flat Pack Low Voltage Differential Signal Maximum Time Interval Error Network Element Oven Controlled Crystal Oscillator Phase Build-out Plesiochronous Digital Hierarchy Positive Emitter Coupled Logic Phase and Frequency Detector Phase Locked Loop Power-On Reset parts per billion parts per million peak-to-peak root-mean-square Read Only Read/Write Synchronous Digital Hierarchy SDH/SONET Equipment Clock Synchronous Equipment Timing source Synchronous Optical Network Synchronization Supply Unit Synchronous Transport Module Time Deviation Temperature Compensated Crystal Oscillator Unit Interval Crystal Oscillator [2] AT & T 62411 (12/1990) ACCUNET(R) T1.5 Service description and Interface Specification [3] ETSI ETS 300 462-3, (01/1997) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 3: The control of jitter and wander within synchronization networks [4] ETSI ETS 300 462-5 (09/1996) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment [5] IEEE 1149.1 (1990) Standard Test Access Port and Boundary-Scan Architecture [6] ITU-T G.703 (10/1998) Physical/electrical characteristics of hierarchical digital interfaces [7] ITU-T G.736 (03/1993) Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s [8] ITU-T G.742 (1988) Second order digital multiplex equipment operating at 8448 kbit/s, and using positive justification [9] ITU-T G.783 (10/2000) Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks [10] ITU-T G.812 (06/1998) Timing requirements of slave clocks suitable for use as node clocks in synchronization networks [11] ITU-T G.813 (08/1996) Timing characteristics of SDH equipment slave clocks (SEC) [12] ITU-T G.822 (11/1988) Controlled slip rate objectives on an international digital connection [13] ITU-T G.823 (03/2000) The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Revision 5/November 2006 (c) Semtech Corp. Page 115 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS [14] ITU-T G.824 (03/2000) The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy [15] ITU-T G.825 (03/2000) The control of jitter and wander within digital networks which are based on the Synchronous Digital Hierarchy (SDH) [16] ITU-T K.41 (05/1998) Resistability of internal interfaces of telecommunication centres to surge overvoltages [17] Telcordia GR-253-CORE, Issue 3 (09/ 2000) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [18] Telcordia GR-499-CORE, Issue 2 (12/1998) Transport Systems Generic Requirements (TSGR) Common requirements [19] Telcordia GR-1244-CORE, Issue 2 (12/2000) Clocks for the Synchronized Network: Common Generic Criteria FINAL DATASHEET Trademark Acknowledgements Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. ACCUNET(R) is a registered trademark of AT & T. C-MAC is a registered trademark of C-MAC MicroTechnology - a division of Solectron Corporation. ICT Flexacom is a registered trademark of ICT Electronics. Motorola is a registered trademark of Motorola, Inc. Telcordia is a registered trademark of Telcordia Technologies. Revision 5/November 2006 (c) Semtech Corp. Page 116 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Revision Status/History FINAL DATASHEET The Revision Status of the datasheet, as shown in the center of the datasheet header bar, may be TARGET, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet) within the design cycle. TARGET status is used when the design is being realized but is not yet physically available, and the datasheet content reflects the intention of the design. The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the datasheet content more accurately represents the realization of the design. The datasheet is only raised to FINAL status after Table 32 Revision History Revision 0.02/October 2002 1.00/October 2002 1.01/November 2002 2.00/April 2003 2.01/May 2003 All pages Pages 9, 10, 18, and Reg. 22 "ESD Protection" on page 105 "Latchup Protection" on page 105 3.00/October 2003 All pages Reg. 09, 34, 3D, 3E, 71 Table 3, Table 5, Table 16, Table 25, Table 26, Table 32 and Figure 17. Reference See particular revision the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a FINAL release (Revision 5) of the ACS8522 datasheet. Changes made for this document revision are given in Table 32, together with a summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the datasheet. Description of Changes Initial release of Preliminary datasheet. First public release of Preliminary datasheet. Minor update. Major revision. First release at FINAL status. References to input frequencies 155 MHz and 311 MHz removed (not supported). New Sections added. Major revision. All pages reformatted. General update of crossreferences. Register descriptions updated. Tables and Figures updated. "Crystal Frequency Calibration" on page 20, Sections updated. "Input-to-Output Phase Adjustment" on page 24, "Register Map" on page 41, and "Revision Status/History" on page 117. 3.01/October 2006 "References" Section Figure 15 and Figure 16 Para 1 on page 19 Back page "Trademark Acknowledgements" Section Front page, "Abbreviations" Section and back page 5/November 2006 All pages Typographic changes. Termination figures redrawn. Phase detector now patented. Semtech US Address updated. Semtech Taiwan address changed Change to trademarks. References added to availability of lead (Pb)-free packaged variant (ACS8522T). Semtech Single-digit revision numbering scheme now used for Adv. Comms. datasheets,which redefines this document as being at Rev. 5. Revision 5/November 2006 (c) Semtech Corp. Page 117 www.semtech.com ACS8522 SETS LITE ADVANCED COMMUNICATIONS Ordering Information Table 33 Parts List Part Number ACS8522 ACS8522T Description SETS LITE Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems Lead (Pb)-free version available (ACS8522T), RoHS and WEEE compliant. FINAL DATASHEET Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User's implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards. Contacts For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: Internet: USA: sales@semtech.com http://www.semtech.com 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 acsupport@semtech.com FAR EAST: 12F, No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601 ISO9001 CERTIFIED Revision 5/November 2006 (c) Semtech Corp. Page 118 www.semtech.com |
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